PWRMGR Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	29.274us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	63.990us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	39.087us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.730s	1.612ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	289.059us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.460s	52.686us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	39.087us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	289.059us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.410s	273.965us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.410s	273.965us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.130s	33.827us	50	50	100.00
		pwrmgr_lowpower_invalid	0.810s	43.427us	49	50	98.00
V2	reset	pwrmgr_reset	1.020s	80.284us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	114.130us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	80.284us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.720s	342.896us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	290.382us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.890s	67.419us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.000s	2.370ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	56.331us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.580s	528.228us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.580s	528.228us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	63.990us	5	5	100.00
		pwrmgr_csr_rw	0.710s	39.087us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	289.059us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	46.898us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	63.990us	5	5	100.00
		pwrmgr_csr_rw	0.710s	39.087us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	289.059us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	46.898us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.080s	1.237ms	20	20	100.00
		pwrmgr_sec_cm	2.350s	659.703us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.350s	659.703us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.350s	659.703us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.080s	1.237ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.360s	802.014us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.500s	895.344us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	74.143us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	28.738us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.350s	659.703us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.350s	659.703us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.350s	659.703us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	50.349us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	61.522us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.470s	348.532us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	39.087us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	39.087us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	159.404us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	35.880s	9.225ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 16.pwrmgr_wakeup_reset.27174071837268107680262737466146758761167419313327825873872948777994451583106
      Line 388, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 32.pwrmgr_lowpower_invalid.114318570353405996861860589637111537101088470598006341596989979906803673901519
      Line 251, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  48107336 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  48107336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 42.pwrmgr_escalation_timeout.14411306775816318012509489051245993033252523301349648241102851194260168684613
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  98559371 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  98559371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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