PWRMGR Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.800s 35.315us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.680s 48.191us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 59.208us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.030s 329.561us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.040s 160.431us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.350s 168.474us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 59.208us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 160.431us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.360s 269.848us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.360s 269.848us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.160s 36.486us 50 50 100.00
pwrmgr_lowpower_invalid 0.810s 42.234us 50 50 100.00
V2 reset pwrmgr_reset 1.030s 90.774us 50 50 100.00
pwrmgr_reset_invalid 1.140s 99.714us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.030s 90.774us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.600s 294.941us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.330s 257.345us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.900s 65.200us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.500s 1.647ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.690s 18.061us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.650s 121.533us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.650s 121.533us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.680s 48.191us 5 5 100.00
pwrmgr_csr_rw 0.720s 59.208us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 160.431us 5 5 100.00
pwrmgr_same_csr_outstanding 0.960s 157.857us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.680s 48.191us 5 5 100.00
pwrmgr_csr_rw 0.720s 59.208us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 160.431us 5 5 100.00
pwrmgr_same_csr_outstanding 0.960s 157.857us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.750s 209.218us 20 20 100.00
pwrmgr_sec_cm 2.150s 601.465us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.150s 601.465us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.150s 601.465us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.750s 209.218us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.380s 884.927us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.590s 884.398us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.070s 76.029us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.690s 29.761us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.150s 601.465us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.150s 601.465us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.150s 601.465us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 46.874us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.720s 52.013us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.470s 290.350us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 59.208us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 59.208us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.080s 603.018us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 42.420s 12.646ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Past Results