PWRMGR Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.750s 167.017us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.730s 34.651us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.710s 21.747us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.450s 1.268ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.960s 25.804us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.320s 141.669us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.710s 21.747us 20 20 100.00
pwrmgr_csr_aliasing 0.960s 25.804us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.230s 212.463us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.230s 212.463us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.060s 33.612us 50 50 100.00
pwrmgr_lowpower_invalid 0.820s 45.312us 50 50 100.00
V2 reset pwrmgr_reset 1.050s 88.842us 50 50 100.00
pwrmgr_reset_invalid 1.140s 110.528us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.050s 88.842us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.530s 320.208us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.520s 305.335us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.900s 65.229us 50 50 100.00
V2 stress_all pwrmgr_stress_all 8.160s 3.123ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.830s 43.556us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 3.140s 1.386ms 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 3.140s 1.386ms 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.730s 34.651us 5 5 100.00
pwrmgr_csr_rw 0.710s 21.747us 20 20 100.00
pwrmgr_csr_aliasing 0.960s 25.804us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 42.756us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.730s 34.651us 5 5 100.00
pwrmgr_csr_rw 0.710s 21.747us 20 20 100.00
pwrmgr_csr_aliasing 0.960s 25.804us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 42.756us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.880s 606.054us 20 20 100.00
pwrmgr_sec_cm 1.710s 720.319us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.710s 720.319us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.710s 720.319us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.880s 606.054us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.450s 884.899us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.360s 854.550us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.020s 65.985us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.670s 31.827us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.710s 720.319us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.710s 720.319us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.710s 720.319us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 51.467us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.720s 56.709us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.360s 274.265us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.710s 21.747us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.710s 21.747us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.040s 500.893us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 36.730s 11.084ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Past Results