PWRMGR Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	30.663us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	45.906us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	21.170us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.610s	488.514us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	250.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.640s	97.001us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	21.170us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	250.908us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.300s	215.704us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.300s	215.704us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.100s	32.435us	50	50	100.00
		pwrmgr_lowpower_invalid	0.820s	40.701us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	80.133us	50	50	100.00
		pwrmgr_reset_invalid	1.130s	101.464us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	80.133us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.520s	338.318us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.390s	298.129us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	59.909us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.610s	2.082ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	25.093us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.720s	2.500ms	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.720s	2.500ms	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	45.906us	5	5	100.00
		pwrmgr_csr_rw	0.690s	21.170us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	250.908us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	53.091us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	45.906us	5	5	100.00
		pwrmgr_csr_rw	0.690s	21.170us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	250.908us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	53.091us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	391.712us	20	20	100.00
		pwrmgr_sec_cm	1.520s	315.691us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.520s	315.691us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.520s	315.691us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	391.712us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.350s	864.506us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.350s	898.950us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.030s	75.454us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	29.658us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.520s	315.691us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.520s	315.691us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.520s	315.691us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	56.294us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	57.420us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.410s	270.813us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	21.170us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	21.170us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.030s	161.870us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	32.710s	11.684ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.58389915771742253907084462526604809603126411771648765523406716736958874376268
      Line 1380, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 10469494827 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 10469494827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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