PWRMGR Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	28.343us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	45.782us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	71.441us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.440s	5.258ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.840s	128.770us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.340s	109.628us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	71.441us	20	20	100.00
		pwrmgr_csr_aliasing	0.840s	128.770us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.360s	301.205us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.360s	301.205us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.110s	33.170us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	44.943us	50	50	100.00
V2	reset	pwrmgr_reset	1.000s	87.027us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	110.219us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.000s	87.027us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.570s	317.199us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.440s	306.627us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.850s	68.174us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.850s	1.786ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	32.263us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.410s	211.953us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.410s	211.953us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	45.782us	5	5	100.00
		pwrmgr_csr_rw	0.740s	71.441us	20	20	100.00
		pwrmgr_csr_aliasing	0.840s	128.770us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	72.668us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	45.782us	5	5	100.00
		pwrmgr_csr_rw	0.740s	71.441us	20	20	100.00
		pwrmgr_csr_aliasing	0.840s	128.770us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	72.668us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.680s	209.594us	20	20	100.00
		pwrmgr_sec_cm	2.180s	662.506us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.180s	662.506us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.180s	662.506us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.680s	209.594us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.250s	877.953us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.380s	918.866us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	67.267us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	28.826us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.180s	662.506us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.180s	662.506us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.180s	662.506us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.760s	48.706us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.780s	47.217us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.370s	275.103us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	71.441us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	71.441us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	653.267us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	33.900s	10.944ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 23.pwrmgr_stress_all_with_rand_reset.41386829432378953437602248700788304588262269933971242347560253716585945518157
      Line 3078, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 12821674284 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 12821674284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 33.pwrmgr_wakeup_reset.104320404191222996386388318278779553979992608597682397050173901300082909703366
      Line 357, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!fast_is_active) || (usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i)))' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 44.pwrmgr_stress_all_with_rand_reset.5741344809904224416691127685639043966416965570922635512597016726507144256093
      Line 3322, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((!fast_is_active) || (usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i)))'
        UVM_ERROR @ 13372974734 ps: (pwrmgr_clock_enables_sva_if.sv:50) [ASSERT FAILED] UsbClkActive_A
        UVM_INFO @ 13372974734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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