PWRMGR Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.850s 31.713us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.690s 27.388us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.740s 23.355us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.670s 3.817ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.040s 51.535us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.180s 40.434us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.740s 23.355us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 51.535us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.400s 272.789us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.400s 272.789us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.140s 30.407us 50 50 100.00
pwrmgr_lowpower_invalid 0.790s 45.724us 50 50 100.00
V2 reset pwrmgr_reset 1.100s 83.263us 50 50 100.00
pwrmgr_reset_invalid 1.120s 111.052us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.100s 83.263us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.410s 275.333us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.370s 270.508us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.890s 59.899us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.290s 1.823ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.740s 17.975us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.970s 130.500us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.970s 130.500us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.690s 27.388us 5 5 100.00
pwrmgr_csr_rw 0.740s 23.355us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 51.535us 5 5 100.00
pwrmgr_same_csr_outstanding 0.950s 50.426us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.690s 27.388us 5 5 100.00
pwrmgr_csr_rw 0.740s 23.355us 20 20 100.00
pwrmgr_csr_aliasing 1.040s 51.535us 5 5 100.00
pwrmgr_same_csr_outstanding 0.950s 50.426us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.740s 733.551us 20 20 100.00
pwrmgr_sec_cm 2.080s 674.957us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.080s 674.957us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.080s 674.957us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.740s 733.551us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.340s 836.063us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.650s 774.218us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.010s 78.683us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.690s 30.335us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.080s 674.957us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.080s 674.957us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.080s 674.957us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.700s 41.816us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.790s 55.880us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.270s 275.403us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.740s 23.355us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.740s 23.355us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.090s 2.114ms 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 43.370s 12.694ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Past Results