V1 |
smoke |
pwrmgr_smoke |
0.770s |
32.577us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
pwrmgr_csr_hw_reset |
0.680s |
154.965us |
5 |
5 |
100.00 |
V1 |
csr_rw |
pwrmgr_csr_rw |
0.730s |
25.366us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
pwrmgr_csr_bit_bash |
3.050s |
223.674us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
pwrmgr_csr_aliasing |
0.940s |
210.916us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
pwrmgr_csr_mem_rw_with_rand_reset |
1.550s |
122.508us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
pwrmgr_csr_rw |
0.730s |
25.366us |
20 |
20 |
100.00 |
|
|
pwrmgr_csr_aliasing |
0.940s |
210.916us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
wakeup |
pwrmgr_wakeup |
1.370s |
244.044us |
50 |
50 |
100.00 |
V2 |
control_clks |
pwrmgr_wakeup |
1.370s |
244.044us |
50 |
50 |
100.00 |
V2 |
aborted_low_power |
pwrmgr_aborted_low_power |
1.070s |
33.756us |
50 |
50 |
100.00 |
|
|
pwrmgr_lowpower_invalid |
0.770s |
78.614us |
50 |
50 |
100.00 |
V2 |
reset |
pwrmgr_reset |
1.010s |
120.449us |
50 |
50 |
100.00 |
|
|
pwrmgr_reset_invalid |
1.170s |
105.482us |
50 |
50 |
100.00 |
V2 |
main_power_glitch_reset |
pwrmgr_reset |
1.010s |
120.449us |
50 |
50 |
100.00 |
V2 |
reset_wakeup_race |
pwrmgr_wakeup_reset |
1.450s |
279.324us |
50 |
50 |
100.00 |
V2 |
lowpower_wakeup_race |
pwrmgr_lowpower_wakeup_race |
1.330s |
290.093us |
50 |
50 |
100.00 |
V2 |
disable_rom_integrity_check |
pwrmgr_disable_rom_integrity_check |
0.940s |
63.226us |
50 |
50 |
100.00 |
V2 |
stress_all |
pwrmgr_stress_all |
6.620s |
1.959ms |
50 |
50 |
100.00 |
V2 |
intr_test |
pwrmgr_intr_test |
0.690s |
20.482us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
pwrmgr_tl_errors |
2.970s |
174.819us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
pwrmgr_tl_errors |
2.970s |
174.819us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
pwrmgr_csr_hw_reset |
0.680s |
154.965us |
5 |
5 |
100.00 |
|
|
pwrmgr_csr_rw |
0.730s |
25.366us |
20 |
20 |
100.00 |
|
|
pwrmgr_csr_aliasing |
0.940s |
210.916us |
5 |
5 |
100.00 |
|
|
pwrmgr_same_csr_outstanding |
0.940s |
68.306us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
pwrmgr_csr_hw_reset |
0.680s |
154.965us |
5 |
5 |
100.00 |
|
|
pwrmgr_csr_rw |
0.730s |
25.366us |
20 |
20 |
100.00 |
|
|
pwrmgr_csr_aliasing |
0.940s |
210.916us |
5 |
5 |
100.00 |
|
|
pwrmgr_same_csr_outstanding |
0.940s |
68.306us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
540 |
540 |
100.00 |
V2S |
tl_intg_err |
pwrmgr_tl_intg_err |
1.720s |
188.468us |
20 |
20 |
100.00 |
|
|
pwrmgr_sec_cm |
1.710s |
777.627us |
5 |
5 |
100.00 |
V2S |
prim_count_check |
pwrmgr_sec_cm |
1.710s |
777.627us |
5 |
5 |
100.00 |
V2S |
prim_fsm_check |
pwrmgr_sec_cm |
1.710s |
777.627us |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
pwrmgr_tl_intg_err |
1.720s |
188.468us |
20 |
20 |
100.00 |
V2S |
sec_cm_lc_ctrl_intersig_mubi |
pwrmgr_sec_cm_lc_ctrl_intersig_mubi |
3.120s |
807.615us |
49 |
50 |
98.00 |
V2S |
sec_cm_rom_ctrl_intersig_mubi |
pwrmgr_sec_cm_rom_ctrl_intersig_mubi |
3.680s |
889.364us |
50 |
50 |
100.00 |
V2S |
sec_cm_rstmgr_intersig_mubi |
pwrmgr_sec_cm_rstmgr_intersig_mubi |
0.990s |
68.719us |
50 |
50 |
100.00 |
V2S |
sec_cm_esc_rx_clk_bkgn_chk |
pwrmgr_esc_clk_rst_malfunc |
0.680s |
31.539us |
50 |
50 |
100.00 |
V2S |
sec_cm_esc_rx_clk_local_esc |
pwrmgr_sec_cm |
1.710s |
777.627us |
5 |
5 |
100.00 |
V2S |
sec_cm_fsm_sparse |
pwrmgr_sec_cm |
1.710s |
777.627us |
5 |
5 |
100.00 |
V2S |
sec_cm_fsm_terminal |
pwrmgr_sec_cm |
1.710s |
777.627us |
5 |
5 |
100.00 |
V2S |
sec_cm_ctrl_flow_global_esc |
pwrmgr_global_esc |
0.690s |
35.430us |
50 |
50 |
100.00 |
V2S |
sec_cm_main_pd_rst_local_esc |
pwrmgr_glitch |
0.720s |
54.065us |
50 |
50 |
100.00 |
V2S |
sec_cm_ctrl_config_regwen |
pwrmgr_sec_cm_ctrl_config_regwen |
1.260s |
216.066us |
50 |
50 |
100.00 |
V2S |
sec_cm_wakeup_config_regwen |
pwrmgr_csr_rw |
0.730s |
25.366us |
20 |
20 |
100.00 |
V2S |
sec_cm_reset_config_regwen |
pwrmgr_csr_rw |
0.730s |
25.366us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
374 |
375 |
99.73 |
V3 |
escalation_timeout |
pwrmgr_escalation_timeout |
1.060s |
167.541us |
50 |
50 |
100.00 |
V3 |
stress_all_with_rand_reset |
pwrmgr_stress_all_with_rand_reset |
41.830s |
13.948ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
100 |
100 |
100.00 |
|
|
TOTAL |
|
|
1119 |
1120 |
99.91 |