PWRMGR Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	63.312us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.770s	32.723us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.740s	22.822us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.580s	483.634us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	167.418us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.220s	91.165us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.740s	22.822us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	167.418us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.370s	233.826us	49	50	98.00
V2	control_clks	pwrmgr_wakeup	1.370s	233.826us	49	50	98.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.100s	33.737us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	83.053us	50	50	100.00
V2	reset	pwrmgr_reset	0.990s	76.752us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	106.891us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.990s	76.752us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.620s	329.359us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.510s	310.261us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.870s	52.410us	48	50	96.00
V2	stress_all	pwrmgr_stress_all	7.080s	2.040ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.700s	24.183us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.600s	136.980us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.600s	136.980us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.770s	32.723us	5	5	100.00
		pwrmgr_csr_rw	0.740s	22.822us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	167.418us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	126.010us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.770s	32.723us	5	5	100.00
		pwrmgr_csr_rw	0.740s	22.822us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	167.418us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	126.010us	20	20	100.00
V2		TOTAL			537	540	99.44
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.810s	233.440us	20	20	100.00
		pwrmgr_sec_cm	2.190s	660.782us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.190s	660.782us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.190s	660.782us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.810s	233.440us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.450s	854.548us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.470s	858.075us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	67.406us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	28.884us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.190s	660.782us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.190s	660.782us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.190s	660.782us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	49.038us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	54.335us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.320s	259.798us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.740s	22.822us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.740s	22.822us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	161.103us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	39.630s	13.125ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 2 failures:

  • Test pwrmgr_disable_rom_integrity_check has 2 failures.

    • 16.pwrmgr_disable_rom_integrity_check.72700022998169580635231037022736043248298511722835853688317922978257562791300
      Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  35929627 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  35929627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.pwrmgr_disable_rom_integrity_check.43493289059840333113306004300650588505190769682944571316489781487134613222735
      Line 288, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  42057128 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  42057128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:752) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 10.pwrmgr_stress_all_with_rand_reset.84715740495592712949538903428344852569276550516750801617433514295528142419061
      Line 2699, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3153851217 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3153851217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup has 1 failures.

    • 16.pwrmgr_wakeup.34592453990671525715423487232593432249435042883651204227884564131973216070720
      Line 370, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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