PWRMGR Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	33.301us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	79.549us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.800s	22.695us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.350s	4.106ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	286.729us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.300s	60.887us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.800s	22.695us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	286.729us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.410s	231.278us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.410s	231.278us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.070s	34.535us	50	50	100.00
		pwrmgr_lowpower_invalid	0.840s	45.781us	50	50	100.00
V2	reset	pwrmgr_reset	1.070s	80.921us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	93.819us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.070s	80.921us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.510s	296.846us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.420s	294.962us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	48.154us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.700s	1.837ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.760s	29.359us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.810s	471.387us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.810s	471.387us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	79.549us	5	5	100.00
		pwrmgr_csr_rw	0.800s	22.695us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	286.729us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	45.963us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	79.549us	5	5	100.00
		pwrmgr_csr_rw	0.800s	22.695us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	286.729us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	45.963us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	173.133us	20	20	100.00
		pwrmgr_sec_cm	2.160s	683.236us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.160s	683.236us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.160s	683.236us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	173.133us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.290s	816.211us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.380s	885.807us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.070s	74.786us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	39.704us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.160s	683.236us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.160s	683.236us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.160s	683.236us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.760s	50.337us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	55.805us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.320s	251.607us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.800s	22.695us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.800s	22.695us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	171.788us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	32.400s	9.222ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_lowpower_wakeup_race has 1 failures.

    • 4.pwrmgr_lowpower_wakeup_race.107120079386364504279683534274797255036243227710624354415320747246760402229450
      Line 352, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 46.pwrmgr_escalation_timeout.27746954626039057387709200167259994472044844810006011612381860157333321537682
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  93990717 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  93990717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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