PWRMGR Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	30.750us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.720s	31.376us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.760s	24.345us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.340s	1.263ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.840s	32.619us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.080s	122.092us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.760s	24.345us	20	20	100.00
		pwrmgr_csr_aliasing	0.840s	32.619us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.380s	290.905us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.380s	290.905us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.120s	37.908us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	68.037us	50	50	100.00
V2	reset	pwrmgr_reset	1.070s	104.918us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	106.005us	49	50	98.00
V2	main_power_glitch_reset	pwrmgr_reset	1.070s	104.918us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.580s	322.514us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.470s	310.676us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	51.130us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.160s	1.757ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	19.153us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.630s	272.407us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.630s	272.407us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.720s	31.376us	5	5	100.00
		pwrmgr_csr_rw	0.760s	24.345us	20	20	100.00
		pwrmgr_csr_aliasing	0.840s	32.619us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	140.328us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.720s	31.376us	5	5	100.00
		pwrmgr_csr_rw	0.760s	24.345us	20	20	100.00
		pwrmgr_csr_aliasing	0.840s	32.619us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	140.328us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.790s	204.973us	20	20	100.00
		pwrmgr_sec_cm	2.240s	647.921us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.240s	647.921us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.240s	647.921us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.790s	204.973us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.520s	911.727us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.400s	869.477us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.070s	90.790us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	27.943us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.240s	647.921us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.240s	647.921us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.240s	647.921us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	92.822us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	58.974us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.450s	268.052us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.760s	24.345us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.760s	24.345us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.080s	1.171ms	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.130s	12.984ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 20.pwrmgr_stress_all_with_rand_reset.3851742546216736710896863012954640218804320013435340876677535389109430151069
      Line 5086, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
        UVM_ERROR @ 22519991486 ps: (pwrmgr_sec_cm_checker_assert.sv:161) [ASSERT FAILED] RstreqChkMainpd_A
        UVM_INFO @ 22519991486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 27.pwrmgr_reset_invalid.90078862288843126647408529683310869573669769308178804746605467953017804266305
      Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest/run.log

            Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 125086704 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 125086704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 49.pwrmgr_wakeup_reset.70019326972608177699754141971765932939621629874843936830043829712914401440422
      Line 364, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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