PWRMGR Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	36.494us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.720s	56.239us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	50.316us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.530s	419.966us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	156.514us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.300s	54.351us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	50.316us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	156.514us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.200s	224.239us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.200s	224.239us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.000s	31.734us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	44.067us	50	50	100.00
V2	reset	pwrmgr_reset	1.020s	87.062us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	111.847us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	87.062us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.450s	302.355us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.220s	246.324us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	65.123us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.600s	3.047ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.700s	51.979us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.490s	238.373us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.490s	238.373us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.720s	56.239us	5	5	100.00
		pwrmgr_csr_rw	0.710s	50.316us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	156.514us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	153.701us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.720s	56.239us	5	5	100.00
		pwrmgr_csr_rw	0.710s	50.316us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	156.514us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	153.701us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	205.789us	20	20	100.00
		pwrmgr_sec_cm	2.150s	641.015us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.150s	641.015us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.150s	641.015us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	205.789us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.290s	841.760us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.590s	881.913us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.000s	69.916us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	29.297us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.150s	641.015us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.150s	641.015us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.150s	641.015us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	45.712us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.690s	51.161us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.410s	286.842us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	50.316us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	50.316us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	334.446us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	34.820s	14.412ms	49	50	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 6.pwrmgr_stress_all_with_rand_reset.106606947820779791719567141844505200791181264930356685922958698075088594826405
      Line 4677, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 24346409061 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 24346409061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 33.pwrmgr_escalation_timeout.19757032765291322351340021200495163583733472732145407535694520388420335287006
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  96421032 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  96421032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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