PWRMGR Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.760s 26.331us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.680s 42.032us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.770s 35.141us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.100s 216.225us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.990s 61.534us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.450s 128.345us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.770s 35.141us 20 20 100.00
pwrmgr_csr_aliasing 0.990s 61.534us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.310s 257.108us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.310s 257.108us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.000s 80.639us 50 50 100.00
pwrmgr_lowpower_invalid 0.790s 45.214us 50 50 100.00
V2 reset pwrmgr_reset 1.020s 79.207us 50 50 100.00
pwrmgr_reset_invalid 1.110s 92.484us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.020s 79.207us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.710s 341.651us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.370s 318.548us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.920s 65.567us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.980s 2.383ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.720s 17.766us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.550s 106.491us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.550s 106.491us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.680s 42.032us 5 5 100.00
pwrmgr_csr_rw 0.770s 35.141us 20 20 100.00
pwrmgr_csr_aliasing 0.990s 61.534us 5 5 100.00
pwrmgr_same_csr_outstanding 0.910s 473.450us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.680s 42.032us 5 5 100.00
pwrmgr_csr_rw 0.770s 35.141us 20 20 100.00
pwrmgr_csr_aliasing 0.990s 61.534us 5 5 100.00
pwrmgr_same_csr_outstanding 0.910s 473.450us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.730s 192.892us 20 20 100.00
pwrmgr_sec_cm 1.660s 689.214us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.660s 689.214us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.660s 689.214us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.730s 192.892us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.340s 887.843us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.440s 850.063us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.060s 76.968us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.720s 29.081us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.660s 689.214us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.660s 689.214us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.660s 689.214us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 42.820us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.800s 62.401us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.330s 306.870us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.770s 35.141us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.770s 35.141us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.050s 284.652us 49 50 98.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 38.880s 12.815ms 50 50 100.00
V3 TOTAL 99 100 99.00
TOTAL 1119 1120 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Failure Buckets

Past Results