PWRMGR Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.780s 26.550us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.720s 31.868us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.750s 21.124us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.350s 272.477us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.990s 73.064us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.480s 56.704us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.750s 21.124us 20 20 100.00
pwrmgr_csr_aliasing 0.990s 73.064us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.430s 298.588us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.430s 298.588us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.980s 83.825us 50 50 100.00
pwrmgr_lowpower_invalid 0.780s 44.664us 50 50 100.00
V2 reset pwrmgr_reset 1.010s 95.140us 50 50 100.00
pwrmgr_reset_invalid 1.160s 97.122us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.010s 95.140us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.640s 342.508us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.330s 249.608us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.870s 64.435us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.700s 2.218ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.700s 18.022us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.640s 54.772us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.640s 54.772us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.720s 31.868us 5 5 100.00
pwrmgr_csr_rw 0.750s 21.124us 20 20 100.00
pwrmgr_csr_aliasing 0.990s 73.064us 5 5 100.00
pwrmgr_same_csr_outstanding 0.960s 63.039us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.720s 31.868us 5 5 100.00
pwrmgr_csr_rw 0.750s 21.124us 20 20 100.00
pwrmgr_csr_aliasing 0.990s 73.064us 5 5 100.00
pwrmgr_same_csr_outstanding 0.960s 63.039us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.720s 207.905us 20 20 100.00
pwrmgr_sec_cm 2.190s 610.623us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.190s 610.623us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.190s 610.623us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.720s 207.905us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.260s 848.318us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.570s 899.184us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.000s 76.122us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.720s 28.249us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.190s 610.623us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.190s 610.623us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.190s 610.623us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.670s 67.640us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.710s 58.605us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.370s 242.548us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.750s 21.124us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.750s 21.124us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.050s 566.274us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 40.150s 13.978ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1120 1120 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.90 98.23 96.43 99.44 96.00 96.37 100.00 98.85

Past Results