PWRMGR Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	29.758us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.740s	25.029us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	22.797us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.570s	319.477us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.070s	50.379us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.330s	52.483us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	22.797us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	50.379us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.480s	325.141us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.480s	325.141us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.160s	33.566us	50	50	100.00
		pwrmgr_lowpower_invalid	0.820s	44.756us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	90.662us	50	50	100.00
		pwrmgr_reset_invalid	1.220s	109.827us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	90.662us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.540s	334.427us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.360s	313.004us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.930s	52.051us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.400s	2.567ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.700s	51.017us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.660s	291.550us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.660s	291.550us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.740s	25.029us	5	5	100.00
		pwrmgr_csr_rw	0.700s	22.797us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	50.379us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	84.991us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.740s	25.029us	5	5	100.00
		pwrmgr_csr_rw	0.700s	22.797us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	50.379us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	84.991us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.990s	1.192ms	20	20	100.00
		pwrmgr_sec_cm	2.090s	635.517us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.090s	635.517us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.090s	635.517us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.990s	1.192ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.460s	867.164us	48	50	96.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.600s	859.704us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.040s	79.579us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.720s	30.271us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.090s	635.517us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.090s	635.517us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.090s	635.517us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	38.845us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	60.888us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.180s	222.508us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	22.797us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	22.797us	20	20	100.00
V2S		TOTAL			373	375	99.47
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	161.420us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	35.720s	10.606ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 2 failures.

    • 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.62345928837308546597795729828784035038458221857788982568290740838033673178869
      Line 639, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.73492137045755577560931360514869528477596149927294073674957553667310600396259
      Line 655, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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