PWRMGR Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	30.180us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	42.099us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	57.865us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.080s	824.924us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	143.670us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.090s	77.805us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	57.865us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	143.670us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.390s	310.188us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.390s	310.188us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.030s	33.043us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	42.372us	50	50	100.00
V2	reset	pwrmgr_reset	1.000s	91.394us	50	50	100.00
		pwrmgr_reset_invalid	1.180s	110.695us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.000s	91.394us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.510s	305.770us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.480s	315.270us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.930s	58.234us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.270s	1.760ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	106.304us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.610s	541.241us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.610s	541.241us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	42.099us	5	5	100.00
		pwrmgr_csr_rw	0.700s	57.865us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	143.670us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	188.497us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	42.099us	5	5	100.00
		pwrmgr_csr_rw	0.700s	57.865us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	143.670us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	188.497us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.850s	184.403us	20	20	100.00
		pwrmgr_sec_cm	1.470s	921.516us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.470s	921.516us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.470s	921.516us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.850s	184.403us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.330s	841.303us	48	50	96.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.420s	807.101us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	64.700us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	29.129us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.470s	921.516us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.470s	921.516us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.470s	921.516us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	49.214us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	49.573us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.320s	285.190us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	57.865us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	57.865us	20	20	100.00
V2S		TOTAL			373	375	99.47
V3	escalation_timeout	pwrmgr_escalation_timeout	1.100s	161.405us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	42.290s	12.442ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 2 failures.

    • 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.22031054978179059955549114799853755843151586336885948850261478092856377051778
      Line 654, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.43248148506005245235756077669458004381808384510564228522073058683378053554571
      Line 605, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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