PWRMGR Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	30.292us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.800s	44.074us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	19.744us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.320s	214.687us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.020s	443.538us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.670s	56.332us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	19.744us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	443.538us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.410s	237.484us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.410s	237.484us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.160s	34.397us	49	50	98.00
		pwrmgr_lowpower_invalid	0.760s	43.377us	50	50	100.00
V2	reset	pwrmgr_reset	1.070s	87.315us	50	50	100.00
		pwrmgr_reset_invalid	1.170s	104.116us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.070s	87.315us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.470s	289.313us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.420s	253.535us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.000s	69.006us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.060s	2.695ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	62.056us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.830s	503.040us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.830s	503.040us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.800s	44.074us	5	5	100.00
		pwrmgr_csr_rw	0.700s	19.744us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	443.538us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	251.942us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.800s	44.074us	5	5	100.00
		pwrmgr_csr_rw	0.700s	19.744us	20	20	100.00
		pwrmgr_csr_aliasing	1.020s	443.538us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	251.942us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.760s	427.690us	20	20	100.00
		pwrmgr_sec_cm	1.910s	569.563us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.910s	569.563us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.910s	569.563us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.760s	427.690us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.470s	878.986us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.480s	858.242us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	70.001us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	29.994us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.910s	569.563us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.910s	569.563us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.910s	569.563us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	42.321us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	54.639us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.300s	264.669us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	19.744us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	19.744us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.080s	158.790us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.880s	11.746ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• Offending '((!fast_is_active) || (usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i)))' has 1 failures:
  • Test pwrmgr_aborted_low_power has 1 failures.

    • 37.pwrmgr_aborted_low_power.84374335290130333126803446617709180882165815327590601558790887656923337533275
      Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest/run.log

            Offending '((!fast_is_active) || (usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i)))'
        UVM_ERROR @  91024162 ps: (pwrmgr_clock_enables_sva_if.sv:50) [ASSERT FAILED] UsbClkActive_A
        UVM_INFO @  91024162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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