PWRMGR Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	42.457us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.750s	34.844us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	38.208us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.290s	928.036us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	158.119us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.280s	92.701us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	38.208us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	158.119us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.350s	267.604us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.350s	267.604us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.100s	33.409us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	43.870us	50	50	100.00
V2	reset	pwrmgr_reset	1.040s	72.718us	50	50	100.00
		pwrmgr_reset_invalid	1.130s	96.349us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.040s	72.718us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.490s	274.601us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.390s	288.865us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.960s	68.720us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.530s	2.629ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	20.500us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.270s	279.152us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.270s	279.152us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.750s	34.844us	5	5	100.00
		pwrmgr_csr_rw	0.700s	38.208us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	158.119us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.030s	45.345us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.750s	34.844us	5	5	100.00
		pwrmgr_csr_rw	0.700s	38.208us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	158.119us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.030s	45.345us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.490s	493.805us	20	20	100.00
		pwrmgr_sec_cm	2.340s	664.592us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.340s	664.592us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.340s	664.592us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.490s	493.805us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.340s	875.826us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.530s	905.630us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.050s	71.492us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.246us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.340s	664.592us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.340s	664.592us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.340s	664.592us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	34.491us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	57.615us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.400s	244.571us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	38.208us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	38.208us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.940s	218.682us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	20.670s	10.034ms	45	50	90.00
V3		TOTAL			94	100	94.00
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 4 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 4 failures.

    • 5.pwrmgr_stress_all_with_rand_reset.81348872639686126534705617520338625293887248491133423690722215267569278006136
      Line 1020, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1940040389 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1940040389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.pwrmgr_stress_all_with_rand_reset.98137412559681109467078512773712366148774744126362590201056521569061562865228
      Line 1313, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2679253011 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2679253011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 3.pwrmgr_stress_all_with_rand_reset.19334546419826995184368434745376881159078286572580177925391836600177319457345
      Line 5026, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3862539549 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 3862539549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 11.pwrmgr_escalation_timeout.13301102275141044722653778087369360954911687347444872629283431592167670770726
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @ 126485090 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @ 126485090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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