PWRMGR Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	33.558us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.720s	38.661us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	35.684us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.550s	346.741us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	389.218us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.290s	53.945us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	35.684us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	389.218us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.380s	277.936us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.380s	277.936us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.060s	34.742us	50	50	100.00
		pwrmgr_lowpower_invalid	0.860s	46.052us	50	50	100.00
V2	reset	pwrmgr_reset	1.080s	101.689us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	105.935us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.080s	101.689us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.500s	324.855us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.320s	287.364us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	66.203us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.220s	2.158ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.710s	23.063us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.480s	288.351us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.480s	288.351us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.720s	38.661us	5	5	100.00
		pwrmgr_csr_rw	0.730s	35.684us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	389.218us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	30.968us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.720s	38.661us	5	5	100.00
		pwrmgr_csr_rw	0.730s	35.684us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	389.218us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	30.968us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.080s	1.763ms	20	20	100.00
		pwrmgr_sec_cm	2.300s	776.778us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.300s	776.778us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.300s	776.778us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.080s	1.763ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.240s	925.405us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.610s	936.259us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	71.256us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	28.478us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.300s	776.778us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.300s	776.778us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.300s	776.778us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	57.436us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	53.863us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.340s	232.666us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	35.684us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	35.684us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.950s	107.813us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	18.160s	12.981ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 2 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 4.pwrmgr_stress_all_with_rand_reset.108473716692098538173224645773640207247431547765439458666061722699874235436761
      Line 1384, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11573818221 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 11573818221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.pwrmgr_stress_all_with_rand_reset.15735992440681704122780417052117520605287779624270235825462514406779003188540
      Line 861, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10604127225 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 10604127225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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