PWRMGR Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	38.015us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.660s	42.994us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	17.267us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.120s	245.082us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.830s	31.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.590s	114.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	17.267us	20	20	100.00
		pwrmgr_csr_aliasing	0.830s	31.718us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	253.029us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	253.029us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.140s	36.044us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	46.011us	50	50	100.00
V2	reset	pwrmgr_reset	1.070s	83.783us	50	50	100.00
		pwrmgr_reset_invalid	1.180s	100.360us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.070s	83.783us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.390s	282.262us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	339.856us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	63.979us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.450s	2.371ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	20.688us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.740s	479.333us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.740s	479.333us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.660s	42.994us	5	5	100.00
		pwrmgr_csr_rw	0.720s	17.267us	20	20	100.00
		pwrmgr_csr_aliasing	0.830s	31.718us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	43.157us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.660s	42.994us	5	5	100.00
		pwrmgr_csr_rw	0.720s	17.267us	20	20	100.00
		pwrmgr_csr_aliasing	0.830s	31.718us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	43.157us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.770s	250.358us	20	20	100.00
		pwrmgr_sec_cm	2.230s	673.897us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.230s	673.897us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.230s	673.897us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.770s	250.358us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.240s	813.281us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.420s	876.343us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	75.983us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	30.050us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.230s	673.897us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.230s	673.897us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.230s	673.897us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	48.141us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	33.302us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.360s	272.497us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	17.267us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	17.267us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.950s	112.446us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	23.670s	7.670ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 8.pwrmgr_stress_all_with_rand_reset.73536963535627258618174061191214603258794226990771209995145462481105136638592
      Line 848, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1784061850 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1784061850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 19.pwrmgr_stress_all_with_rand_reset.25811151257445347962962686469509503219144970527436038965120479366646164980133
      Line 2447, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3393288126 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 3393288126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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