PWRMGR Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	34.361us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	34.572us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	25.213us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.180s	754.963us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	50.340us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.350s	50.367us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	25.213us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	50.340us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.360s	289.696us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.360s	289.696us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.120s	34.494us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	40.887us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	91.317us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	102.722us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	91.317us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.620s	325.719us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.380s	306.930us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.940s	63.160us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.810s	1.777ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	21.772us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.640s	53.725us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.640s	53.725us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	34.572us	5	5	100.00
		pwrmgr_csr_rw	0.730s	25.213us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	50.340us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	150.424us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	34.572us	5	5	100.00
		pwrmgr_csr_rw	0.730s	25.213us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	50.340us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	150.424us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.790s	203.063us	20	20	100.00
		pwrmgr_sec_cm	2.360s	660.459us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.360s	660.459us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.360s	660.459us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.790s	203.063us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.550s	826.150us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.420s	886.967us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	77.208us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	28.912us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.360s	660.459us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.360s	660.459us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.360s	660.459us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.750s	50.914us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	51.550us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.390s	274.893us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	25.213us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	25.213us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.900s	562.611us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	20.390s	14.618ms	47	50	94.00
V3		TOTAL			96	100	96.00
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 23.pwrmgr_stress_all_with_rand_reset.73885822191468837112011817917823624537985574901406004446778990164288195120296
      Line 1376, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 853024460 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 853024460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 41.pwrmgr_stress_all_with_rand_reset.92594240356656015071725330820738525950248836149924703124243859264336966576974
      Line 5096, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 14617577524 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 14617577524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 45.pwrmgr_escalation_timeout.30423753086094272883283217987985743966463714842593953912523063015155714932387
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  99523181 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  99523181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 45.pwrmgr_stress_all_with_rand_reset.64596065200764966031168647930270325467999555752994094668120876350488242186343
      Line 870, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 554376644 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 554376644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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