PWRMGR Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	57.609us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.730s	44.541us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	18.009us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.250s	213.307us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.050s	40.900us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.260s	44.445us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	18.009us	20	20	100.00
		pwrmgr_csr_aliasing	1.050s	40.900us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.350s	261.544us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.350s	261.544us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.020s	52.675us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	41.509us	50	50	100.00
V2	reset	pwrmgr_reset	1.020s	168.505us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	96.211us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	168.505us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.580s	320.086us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.360s	275.032us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	68.941us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	9.630s	2.411ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.660s	59.847us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.830s	153.540us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.830s	153.540us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.730s	44.541us	5	5	100.00
		pwrmgr_csr_rw	0.710s	18.009us	20	20	100.00
		pwrmgr_csr_aliasing	1.050s	40.900us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	171.698us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.730s	44.541us	5	5	100.00
		pwrmgr_csr_rw	0.710s	18.009us	20	20	100.00
		pwrmgr_csr_aliasing	1.050s	40.900us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	171.698us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.150s	1.597ms	20	20	100.00
		pwrmgr_sec_cm	2.120s	678.457us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.120s	678.457us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.120s	678.457us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.150s	1.597ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.350s	884.799us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.580s	898.060us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	70.849us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.626us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.120s	678.457us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.120s	678.457us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.120s	678.457us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.740s	32.657us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	44.038us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.360s	218.689us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	18.009us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	18.009us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.920s	363.669us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	20.850s	5.265ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 20.pwrmgr_stress_all_with_rand_reset.86203521007012573919681880781595455796403989285570613051387446552859652358657
      Line 1310, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1675401683 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1675401683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.pwrmgr_stress_all_with_rand_reset.70273610282863024255651915424011234722013283953328706447137349573182373172866
      Line 3288, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1939460756 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1939460756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 34.pwrmgr_disable_rom_integrity_check.96017303618335379539406296465677426620937359929175587052400647887166428201982
      Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  26287044 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  26287044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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