PWRMGR Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	30.136us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	29.792us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	20.853us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.200s	895.532us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	219.661us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.130s	62.462us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	20.853us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	219.661us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.440s	260.815us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.440s	260.815us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.140s	36.355us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	45.070us	50	50	100.00
V2	reset	pwrmgr_reset	1.010s	82.673us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	109.072us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.010s	82.673us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.570s	323.354us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.280s	234.776us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.890s	69.266us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.340s	2.006ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.700s	18.371us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.580s	262.040us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.580s	262.040us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	29.792us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.853us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	219.661us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	41.535us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	29.792us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.853us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	219.661us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	41.535us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.680s	2.663ms	20	20	100.00
		pwrmgr_sec_cm	1.590s	746.000us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.590s	746.000us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.590s	746.000us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.680s	2.663ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.280s	851.986us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.530s	922.317us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.000s	83.676us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.720s	30.401us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.590s	746.000us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.590s	746.000us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.590s	746.000us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	44.402us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	29.736us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.280s	291.574us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	20.853us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	20.853us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.930s	160.242us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	26.440s	14.478ms	48	50	96.00
V3		TOTAL			98	100	98.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 27.pwrmgr_stress_all_with_rand_reset.13065302106402575689495380189329097586755280423483521137299078023385906116679
      Line 549, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 508459039 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 508459039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 45.pwrmgr_stress_all_with_rand_reset.16683316613958212824167428101307132119258909794533196991208731451699545741807
      Line 3123, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3527556928 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3527556928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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