PWRMGR Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	29.472us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	27.014us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.680s	35.992us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.850s	276.210us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.010s	42.155us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.520s	114.497us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.680s	35.992us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	42.155us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.370s	270.558us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.370s	270.558us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.070s	33.885us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	45.509us	50	50	100.00
V2	reset	pwrmgr_reset	1.020s	81.487us	50	50	100.00
		pwrmgr_reset_invalid	1.170s	102.068us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	81.487us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.550s	324.473us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	302.123us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	69.646us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.640s	2.275ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	23.407us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.540s	332.235us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.540s	332.235us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	27.014us	5	5	100.00
		pwrmgr_csr_rw	0.680s	35.992us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	42.155us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	48.536us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	27.014us	5	5	100.00
		pwrmgr_csr_rw	0.680s	35.992us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	42.155us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	48.536us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.830s	216.498us	20	20	100.00
		pwrmgr_sec_cm	2.170s	622.987us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.170s	622.987us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.170s	622.987us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.830s	216.498us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.410s	836.154us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.500s	873.029us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.950s	173.171us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	31.540us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.170s	622.987us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.170s	622.987us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.170s	622.987us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.730s	46.029us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	63.876us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.340s	256.072us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.680s	35.992us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.680s	35.992us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.900s	108.220us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	21.060s	5.353ms	45	50	90.00
V3		TOTAL			94	100	94.00
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	98.23	96.58	99.62	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 3 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 3 failures.

    • 16.pwrmgr_stress_all_with_rand_reset.55638094479564943279442371534768943315893746709626081584386910735128708772809
      Line 1743, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 12792603003 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 12792603003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.pwrmgr_stress_all_with_rand_reset.56585662600328004295918823441298163599692173910192606034453283682246950442338
      Line 1450, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 12031723902 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 12031723902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 24.pwrmgr_stress_all_with_rand_reset.24009889304209936651993418808073582566533110620728101585351761812859924871451
      Line 3214, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4270050549 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4270050549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 27.pwrmgr_escalation_timeout.114346971668444539442397632145664474142562607530287837436675059747632039604174
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @ 101315329 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @ 101315329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 41.pwrmgr_stress_all_with_rand_reset.114722878292414546631263981981727656418578398878681529970355887033986173425564
      Line 1759, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1024792639 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 1024792639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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