PWRMGR Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	1.050s	26.439us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	72.683us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.880s	25.300us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.680s	141.957us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	70.713us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.690s	139.895us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.880s	25.300us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	70.713us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.840s	265.893us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.840s	265.893us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.250s	74.982us	50	50	100.00
		pwrmgr_lowpower_invalid	1.130s	55.261us	50	50	100.00
V2	reset	pwrmgr_reset	1.650s	72.776us	50	50	100.00
		pwrmgr_reset_invalid	1.530s	103.835us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.650s	72.776us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	2.530s	337.037us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.910s	322.186us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.230s	60.243us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.550s	1.359ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.870s	20.120us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.640s	713.599us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.640s	713.599us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	72.683us	5	5	100.00
		pwrmgr_csr_rw	0.880s	25.300us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	70.713us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.090s	501.244us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	72.683us	5	5	100.00
		pwrmgr_csr_rw	0.880s	25.300us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	70.713us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.090s	501.244us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.860s	254.183us	20	20	100.00
		pwrmgr_sec_cm	3.150s	680.605us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	3.150s	680.605us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	3.150s	680.605us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.860s	254.183us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	5.210s	793.514us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	6.490s	878.725us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.400s	66.712us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	1.010s	30.690us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	3.150s	680.605us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	3.150s	680.605us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	3.150s	680.605us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	1.020s	49.904us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	1.060s	53.884us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	2.450s	294.834us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.880s	25.300us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.880s	25.300us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.500s	113.958us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	26.350s	6.847ms	46	50	92.00
V3		TOTAL			96	100	96.00
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	98.23	96.58	99.62	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 7.pwrmgr_stress_all_with_rand_reset.56755612912329130745175714825512516637849744095160571261906609317840084499274
      Line 1117, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11739562108 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 11739562108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.pwrmgr_stress_all_with_rand_reset.11470494619066708195401391425349393084841235629822678635001410318610586343888
      Line 650, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11232177013 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 11232177013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!fast_is_active) || (usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i)))' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 0.pwrmgr_stress_all_with_rand_reset.27292719075228616462144461450695804805803014559081556658710485504972709278699
      Line 232, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((!fast_is_active) || (usb_clk_en == (usb_clk_en_active_i | usb_ip_clk_status_i)))'
        UVM_ERROR @ 937486619 ps: (pwrmgr_clock_enables_sva_if.sv:50) [ASSERT FAILED] UsbClkActive_A
        UVM_INFO @ 937486619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 4.pwrmgr_stress_all_with_rand_reset.36930854206461153962875280749653176398271938408753230301666431177341889830026
      Line 1444, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4212729906 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4212729906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.08.20_08.17.28
• 2024.08.19_08.30.37
• 2024.08.18_08.55.35
• 2024.08.17_07.38.27
• 2024.08.16_08.54.06