PWRMGR Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.640s	30.015us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.610s	29.769us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.610s	33.672us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.540s	297.807us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.870s	71.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.460s	115.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.610s	33.672us	20	20	100.00
		pwrmgr_csr_aliasing	0.870s	71.775us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.160s	291.118us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.160s	291.118us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.880s	30.606us	50	50	100.00
		pwrmgr_lowpower_invalid	0.690s	43.083us	50	50	100.00
V2	reset	pwrmgr_reset	0.840s	74.465us	50	50	100.00
		pwrmgr_reset_invalid	0.930s	113.021us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.840s	74.465us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.410s	314.976us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.200s	301.578us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.790s	68.661us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	6.950s	2.019ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.610s	30.036us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.480s	941.593us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.480s	941.593us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.610s	29.769us	5	5	100.00
		pwrmgr_csr_rw	0.610s	33.672us	20	20	100.00
		pwrmgr_csr_aliasing	0.870s	71.775us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.800s	51.677us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.610s	29.769us	5	5	100.00
		pwrmgr_csr_rw	0.610s	33.672us	20	20	100.00
		pwrmgr_csr_aliasing	0.870s	71.775us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.800s	51.677us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.530s	207.120us	20	20	100.00
		pwrmgr_sec_cm	1.870s	629.491us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.870s	629.491us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.870s	629.491us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.530s	207.120us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	2.930s	899.775us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.190s	951.940us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.860s	78.565us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.590s	29.225us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.870s	629.491us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.870s	629.491us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.870s	629.491us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.590s	98.966us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.650s	61.051us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.230s	285.328us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.610s	33.672us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.610s	33.672us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.830s	111.084us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	20.600s	9.755ms	48	50	96.00
V3		TOTAL			97	100	97.00
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	98.23	96.58	99.62	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 14.pwrmgr_disable_rom_integrity_check.25421679196610269259264308080318660554979267125945320185798522591317161159310
      Line 88, in log /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  29935663 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  29935663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 31.pwrmgr_stress_all_with_rand_reset.86740681726882740570964640872688510836993475766111520773383474322017913928438
      Line 533, in log /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 624857955 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 624857955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 36.pwrmgr_stress_all_with_rand_reset.37703830131263253104764656267947129144480009651915481208025893600745010386344
      Line 329, in log /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10145926329 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 10145926329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 40.pwrmgr_escalation_timeout.94131747138629959088584004713567172683511225770102020765148077676754702538682
      Line 64, in log /workspaces/repo/scratch/os_regression_2024_08_22/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @ 104799191 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @ 104799191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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