PWRMGR Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 1.146m 47 50 94.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.630s 39.931us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.820s 143.859us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.220s 1.187ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.930s 107.767us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 48.428s 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.820s 143.859us 20 20 100.00
pwrmgr_csr_aliasing 0.930s 107.767us 5 5 100.00
V1 TOTAL 101 105 96.19
V2 wakeup pwrmgr_wakeup 1.144m 46 50 92.00
V2 control_clks pwrmgr_wakeup 1.144m 46 50 92.00
V2 aborted_low_power pwrmgr_aborted_low_power 54.970s 47 50 94.00
pwrmgr_lowpower_invalid 51.177s 47 50 94.00
V2 reset pwrmgr_reset 1.169m 46 50 92.00
pwrmgr_reset_invalid 51.177s 48 50 96.00
V2 main_power_glitch_reset pwrmgr_reset 1.169m 46 50 92.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 48.676s 47 50 94.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 55.046s 46 50 92.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 48.170s 48 50 96.00
V2 stress_all pwrmgr_stress_all 49.124s 47 50 94.00
V2 intr_test pwrmgr_intr_test 0.780s 26.515us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.440s 104.388us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.440s 104.388us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.630s 39.931us 5 5 100.00
pwrmgr_csr_rw 0.820s 143.859us 20 20 100.00
pwrmgr_csr_aliasing 0.930s 107.767us 5 5 100.00
pwrmgr_same_csr_outstanding 48.430s 19 20 95.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.630s 39.931us 5 5 100.00
pwrmgr_csr_rw 0.820s 143.859us 20 20 100.00
pwrmgr_csr_aliasing 0.930s 107.767us 5 5 100.00
pwrmgr_same_csr_outstanding 48.430s 19 20 95.00
V2 TOTAL 511 540 94.63
V2S tl_intg_err pwrmgr_tl_intg_err 1.670s 181.321us 20 20 100.00
pwrmgr_sec_cm 3.600s 620.592us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 3.600s 620.592us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 3.600s 620.592us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.670s 181.321us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 54.944s 46 50 92.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 54.924s 46 50 92.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 54.436s 47 50 94.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 54.880s 46 50 92.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 3.600s 620.592us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 3.600s 620.592us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 3.600s 620.592us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 48.287s 46 50 92.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 49.329s 47 50 94.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 44.631s 47 50 94.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.820s 143.859us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.820s 143.859us 20 20 100.00
V2S TOTAL 350 375 93.33
V3 escalation_timeout pwrmgr_escalation_timeout 44.703s 46 50 92.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 49.162s 46 50 92.00
V3 TOTAL 92 100 92.00
TOTAL 1054 1120 94.11

Testplan Progress

Items Total Written Passing Progress
V1 6 6 4 66.67
V2 12 12 2 16.67
V2S 9 9 2 22.22
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02

Failure Buckets

Past Results