PWRMGR Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.730s 32.978us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.650s 143.668us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.630s 19.557us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.110s 1.222ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.880s 45.112us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.360s 57.033us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.630s 19.557us 20 20 100.00
pwrmgr_csr_aliasing 0.880s 45.112us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.170s 219.876us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.170s 219.876us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 44.645s 49 50 98.00
pwrmgr_lowpower_invalid 0.770s 104.897us 50 50 100.00
V2 reset pwrmgr_reset 1.050s 76.375us 50 50 100.00
pwrmgr_reset_invalid 1.180s 107.794us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.050s 76.375us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 54.204s 49 50 98.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.330s 308.335us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.910s 68.239us 50 50 100.00
V2 stress_all pwrmgr_stress_all 51.616s 49 50 98.00
V2 intr_test pwrmgr_intr_test 0.660s 21.106us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.250s 201.408us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.250s 201.408us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.650s 143.668us 5 5 100.00
pwrmgr_csr_rw 0.630s 19.557us 20 20 100.00
pwrmgr_csr_aliasing 0.880s 45.112us 5 5 100.00
pwrmgr_same_csr_outstanding 0.830s 35.107us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.650s 143.668us 5 5 100.00
pwrmgr_csr_rw 0.630s 19.557us 20 20 100.00
pwrmgr_csr_aliasing 0.880s 45.112us 5 5 100.00
pwrmgr_same_csr_outstanding 0.830s 35.107us 20 20 100.00
V2 TOTAL 537 540 99.44
V2S tl_intg_err pwrmgr_tl_intg_err 1.480s 203.261us 20 20 100.00
pwrmgr_sec_cm 2.130s 636.147us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.130s 636.147us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.130s 636.147us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.480s 203.261us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 44.646s 47 50 94.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 54.162s 48 50 96.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 42.923s 49 50 98.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 44.560s 48 50 96.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.130s 636.147us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.130s 636.147us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.130s 636.147us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 42.913s 49 50 98.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 42.903s 49 50 98.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 44.569s 48 50 96.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.630s 19.557us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.630s 19.557us 20 20 100.00
V2S TOTAL 363 375 96.80
V3 escalation_timeout pwrmgr_escalation_timeout 42.910s 48 50 96.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 19.880s 4.756ms 47 50 94.00
V3 TOTAL 95 100 95.00
TOTAL 1100 1120 98.21

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 9 9 2 22.22
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.89 98.23 96.58 99.62 96.00 96.37 99.74 98.69

Failure Buckets

Past Results