PWRMGR Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 44.925s 48 50 96.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.660s 38.627us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.640s 19.117us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.050s 4.361ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.940s 25.155us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 0.990s 106.093us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.640s 19.117us 20 20 100.00
pwrmgr_csr_aliasing 0.940s 25.155us 5 5 100.00
V1 TOTAL 103 105 98.10
V2 wakeup pwrmgr_wakeup 45.278s 47 50 94.00
V2 control_clks pwrmgr_wakeup 45.278s 47 50 94.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.030m 46 50 92.00
pwrmgr_lowpower_invalid 44.949s 49 50 98.00
V2 reset pwrmgr_reset 44.918s 48 50 96.00
pwrmgr_reset_invalid 1.690s 110.066us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 44.918s 48 50 96.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.030m 48 50 96.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 44.913s 48 50 96.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 44.839s 49 50 98.00
V2 stress_all pwrmgr_stress_all 44.933s 49 50 98.00
V2 intr_test pwrmgr_intr_test 0.730s 39.498us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.360s 150.014us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.360s 150.014us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.660s 38.627us 5 5 100.00
pwrmgr_csr_rw 0.640s 19.117us 20 20 100.00
pwrmgr_csr_aliasing 0.940s 25.155us 5 5 100.00
pwrmgr_same_csr_outstanding 0.820s 41.534us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.660s 38.627us 5 5 100.00
pwrmgr_csr_rw 0.640s 19.117us 20 20 100.00
pwrmgr_csr_aliasing 0.940s 25.155us 5 5 100.00
pwrmgr_same_csr_outstanding 0.820s 41.534us 20 20 100.00
V2 TOTAL 524 540 97.04
V2S tl_intg_err pwrmgr_tl_intg_err 2.030s 395.707us 20 20 100.00
pwrmgr_sec_cm 3.970s 629.973us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 3.970s 629.973us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 3.970s 629.973us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 2.030s 395.707us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.030m 46 50 92.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 1.029m 47 50 94.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 48.450s 47 50 94.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 48.432s 47 50 94.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 3.970s 629.973us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 3.970s 629.973us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 3.970s 629.973us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 44.854s 48 50 96.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 44.843s 49 50 98.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 44.865s 47 50 94.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.640s 19.117us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.640s 19.117us 20 20 100.00
V2S TOTAL 356 375 94.93
V3 escalation_timeout pwrmgr_escalation_timeout 44.853s 47 50 94.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 44.941s 46 50 92.00
V3 TOTAL 93 100 93.00
TOTAL 1076 1120 96.07

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 12 12 4 33.33
V2S 9 9 2 22.22
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85

Failure Buckets

Past Results