PWRMGR Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 48.559s 49 50 98.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 44.629s 1 5 20.00
V1 csr_rw pwrmgr_csr_rw 44.613s 18 20 90.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 44.599s 4 5 80.00
V1 csr_aliasing pwrmgr_csr_aliasing 44.579s 2 5 40.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 44.548s 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 44.613s 18 20 90.00
pwrmgr_csr_aliasing 44.579s 2 5 40.00
V1 TOTAL 92 105 87.62
V2 wakeup pwrmgr_wakeup 2.330s 256.112us 50 50 100.00
V2 control_clks pwrmgr_wakeup 2.330s 256.112us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.470s 46.432us 50 50 100.00
pwrmgr_lowpower_invalid 48.613s 49 50 98.00
V2 reset pwrmgr_reset 42.757s 49 50 98.00
pwrmgr_reset_invalid 1.730s 101.570us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 42.757s 49 50 98.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 2.410s 286.647us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 42.733s 49 50 98.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 1.420s 70.197us 50 50 100.00
V2 stress_all pwrmgr_stress_all 48.579s 48 50 96.00
V2 intr_test pwrmgr_intr_test 44.649s 46 50 92.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 44.538s 18 20 90.00
V2 tl_d_illegal_access pwrmgr_tl_errors 44.538s 18 20 90.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 44.629s 1 5 20.00
pwrmgr_csr_rw 44.613s 18 20 90.00
pwrmgr_csr_aliasing 44.579s 2 5 40.00
pwrmgr_same_csr_outstanding 44.564s 17 20 85.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 44.629s 1 5 20.00
pwrmgr_csr_rw 44.613s 18 20 90.00
pwrmgr_csr_aliasing 44.579s 2 5 40.00
pwrmgr_same_csr_outstanding 44.564s 17 20 85.00
V2 TOTAL 526 540 97.41
V2S tl_intg_err pwrmgr_tl_intg_err 44.671s 16 20 80.00
pwrmgr_sec_cm 3.180s 807.187us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 3.180s 807.187us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 3.180s 807.187us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 44.671s 16 20 80.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 5.750s 798.186us 48 50 96.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 44.664s 49 50 98.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.510s 65.065us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 44.624s 49 50 98.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 3.180s 807.187us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 3.180s 807.187us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 3.180s 807.187us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 1.060s 47.367us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 43.130s 49 50 98.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 2.220s 299.529us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 44.613s 18 20 90.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 44.613s 18 20 90.00
V2S TOTAL 366 375 97.60
V3 escalation_timeout pwrmgr_escalation_timeout 1.600s 111.291us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 48.594s 46 50 92.00
V3 TOTAL 96 100 96.00
TOTAL 1080 1120 96.43

Testplan Progress

Items Total Written Passing Progress
V1 6 6 0 0.00
V2 12 12 5 41.67
V2S 9 9 4 44.44
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85

Failure Buckets

Past Results