PWRMGR Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 42.612s 49 50 98.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 1.020s 33.147us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.940s 50.692us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 4.810s 556.777us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.420s 50.793us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 2.100s 124.140us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.940s 50.692us 20 20 100.00
pwrmgr_csr_aliasing 1.420s 50.793us 5 5 100.00
V1 TOTAL 104 105 99.05
V2 wakeup pwrmgr_wakeup 1.390s 260.709us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.390s 260.709us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.024m 49 50 98.00
pwrmgr_lowpower_invalid 49.045s 48 50 96.00
V2 reset pwrmgr_reset 1.160s 94.359us 50 50 100.00
pwrmgr_reset_invalid 1.080s 101.823us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.160s 94.359us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 51.392s 49 50 98.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.320s 298.975us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.780s 64.595us 50 50 100.00
V2 stress_all pwrmgr_stress_all 6.550s 1.925ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.900s 19.810us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 3.520s 139.844us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 3.520s 139.844us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 1.020s 33.147us 5 5 100.00
pwrmgr_csr_rw 0.940s 50.692us 20 20 100.00
pwrmgr_csr_aliasing 1.420s 50.793us 5 5 100.00
pwrmgr_same_csr_outstanding 1.280s 126.412us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 1.020s 33.147us 5 5 100.00
pwrmgr_csr_rw 0.940s 50.692us 20 20 100.00
pwrmgr_csr_aliasing 1.420s 50.793us 5 5 100.00
pwrmgr_same_csr_outstanding 1.280s 126.412us 20 20 100.00
V2 TOTAL 536 540 99.26
V2S tl_intg_err pwrmgr_tl_intg_err 2.020s 337.837us 20 20 100.00
pwrmgr_sec_cm 1.550s 916.648us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.550s 916.648us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.550s 916.648us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 2.020s 337.837us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.025m 48 50 96.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 1.025m 48 50 96.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.026m 49 50 98.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 1.026m 49 50 98.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.550s 916.648us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.550s 916.648us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.550s 916.648us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.700s 113.462us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.980s 52.445us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.026m 49 50 98.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.940s 50.692us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.940s 50.692us 20 20 100.00
V2S TOTAL 368 375 98.13
V3 escalation_timeout pwrmgr_escalation_timeout 1.250s 125.061us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 42.609s 49 50 98.00
V3 TOTAL 99 100 99.00
TOTAL 1107 1120 98.84

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 12 12 9 75.00
V2S 9 9 4 44.44
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02

Failure Buckets

Past Results