PWRMGR Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 44.288s 47 50 94.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.640s 41.624us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.690s 19.847us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.760s 215.787us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.890s 146.274us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.560s 190.002us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.690s 19.847us 20 20 100.00
pwrmgr_csr_aliasing 0.890s 146.274us 5 5 100.00
V1 TOTAL 102 105 97.14
V2 wakeup pwrmgr_wakeup 58.307s 46 50 92.00
V2 control_clks pwrmgr_wakeup 58.307s 46 50 92.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.136m 47 50 94.00
pwrmgr_lowpower_invalid 1.203m 48 50 96.00
V2 reset pwrmgr_reset 1.224m 46 50 92.00
pwrmgr_reset_invalid 1.038m 49 50 98.00
V2 main_power_glitch_reset pwrmgr_reset 1.224m 46 50 92.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 54.170s 48 50 96.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 58.324s 47 50 94.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 1.038m 47 50 94.00
V2 stress_all pwrmgr_stress_all 44.291s 48 50 96.00
V2 intr_test pwrmgr_intr_test 0.720s 19.162us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.460s 485.573us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.460s 485.573us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.640s 41.624us 5 5 100.00
pwrmgr_csr_rw 0.690s 19.847us 20 20 100.00
pwrmgr_csr_aliasing 0.890s 146.274us 5 5 100.00
pwrmgr_same_csr_outstanding 0.900s 123.060us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.640s 41.624us 5 5 100.00
pwrmgr_csr_rw 0.690s 19.847us 20 20 100.00
pwrmgr_csr_aliasing 0.890s 146.274us 5 5 100.00
pwrmgr_same_csr_outstanding 0.900s 123.060us 20 20 100.00
V2 TOTAL 516 540 95.56
V2S tl_intg_err pwrmgr_tl_intg_err 2.040s 211.708us 20 20 100.00
pwrmgr_sec_cm 2.050s 649.428us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.050s 649.428us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.050s 649.428us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 2.040s 211.708us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.136m 47 50 94.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 54.129s 47 50 94.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 58.887s 47 50 94.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 49.972s 48 50 96.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.050s 649.428us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.050s 649.428us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.050s 649.428us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 59.201s 48 50 96.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 42.787s 49 50 98.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.184m 47 50 94.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.690s 19.847us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.690s 19.847us 20 20 100.00
V2S TOTAL 358 375 95.47
V3 escalation_timeout pwrmgr_escalation_timeout 44.241s 48 50 96.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 1.203m 47 50 94.00
V3 TOTAL 95 100 95.00
TOTAL 1071 1120 95.62

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 12 12 3 25.00
V2S 9 9 2 22.22
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85

Failure Buckets

Past Results