PWRMGR Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	29.184s		49	50	98.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.950s	59.138us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.960s	18.787us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.500s	542.916us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.400s	41.892us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.490s	54.246us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.960s	18.787us	20	20	100.00
		pwrmgr_csr_aliasing	1.400s	41.892us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	wakeup	pwrmgr_wakeup	29.597s		49	50	98.00
V2	control_clks	pwrmgr_wakeup	29.597s		49	50	98.00
V2	aborted_low_power	pwrmgr_aborted_low_power	29.872s		49	50	98.00
		pwrmgr_lowpower_invalid	1.060s	51.059us	50	50	100.00
V2	reset	pwrmgr_reset	29.320s		49	50	98.00
		pwrmgr_reset_invalid	1.520s	111.153us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	29.320s		49	50	98.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	29.731s		49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	29.456s		49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.290s	71.818us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	29.021s		49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.920s	19.439us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.430s	50.179us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.430s	50.179us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.950s	59.138us	5	5	100.00
		pwrmgr_csr_rw	0.960s	18.787us	20	20	100.00
		pwrmgr_csr_aliasing	1.400s	41.892us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.230s	62.034us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.950s	59.138us	5	5	100.00
		pwrmgr_csr_rw	0.960s	18.787us	20	20	100.00
		pwrmgr_csr_aliasing	1.400s	41.892us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.230s	62.034us	20	20	100.00
V2		TOTAL			534	540	98.89
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.920s	224.708us	20	20	100.00
		pwrmgr_sec_cm	2.870s	686.317us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.870s	686.317us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.870s	686.317us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.920s	224.708us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	30.014s		48	50	96.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.940s	777.255us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.530s	73.538us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	30.066s		49	50	98.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.870s	686.317us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.870s	686.317us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.870s	686.317us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	30.361s		49	50	98.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	1.000s	53.259us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	30.216s		49	50	98.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.960s	18.787us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.960s	18.787us	20	20	100.00
V2S		TOTAL			370	375	98.67
V3	escalation_timeout	pwrmgr_escalation_timeout	1.530s	122.947us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.862s		47	50	94.00
V3		TOTAL			97	100	97.00
		TOTAL			1105	1120	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	12	12	6	50.00
V2S	9	9	5	55.56
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.62	96.00	96.37	100.00	98.85

Failure Buckets

Job returned non-zero exit code has 12 failures:

Test pwrmgr_stress_all has 1 failures.

14.pwrmgr_stress_all.61752028592807629026781000259549935546586797462786740210355887789478235789623
Log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 11 05:40 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_smoke has 1 failures.

15.pwrmgr_smoke.66995632387806439447356850999187368249135412030471339416124893587759604254077
Log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 11 05:40 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_reset has 1 failures.

15.pwrmgr_reset.59211927245136937013962742492139923527516169994913924352730948844772509600119
Log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/15.pwrmgr_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 11 05:40 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_lowpower_wakeup_race has 1 failures.

15.pwrmgr_lowpower_wakeup_race.67771072435301362836500340613051662864924595833975281369454612207745784855747
Log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 11 05:40 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test pwrmgr_wakeup has 1 failures.

15.pwrmgr_wakeup.18360078010813630350451152457814570147994063550619846670882024692208567970886
Log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 11 05:40 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 7 more tests.

UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 33.pwrmgr_stress_all_with_rand_reset.37706606593692196186618782149096418721073940346085434967082573701072628689683
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10006935354 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
  UVM_INFO @ 10006935354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 36.pwrmgr_stress_all_with_rand_reset.19873572116303637223729111859935423953649590072108748719794713194295557978261
    Line 702, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 986203259 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 986203259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.
  - 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.91746856210528761437121615258965934233850930145538232147829980011253079451668
    Line 467, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
```
  UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```