PWRMGR Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	1.080s	33.227us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	1.020s	24.441us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.960s	63.276us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.250s	216.598us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.120s	142.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.700s	57.443us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.960s	63.276us	20	20	100.00
		pwrmgr_csr_aliasing	1.120s	142.202us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	2.370s	295.883us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	2.370s	295.883us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.740s	34.779us	50	50	100.00
		pwrmgr_lowpower_invalid	1.200s	43.821us	50	50	100.00
V2	reset	pwrmgr_reset	1.590s	93.813us	50	50	100.00
		pwrmgr_reset_invalid	1.800s	102.390us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.590s	93.813us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	2.460s	282.402us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	2.130s	258.092us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.340s	53.852us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	10.710s	2.792ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.890s	17.381us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.690s	103.975us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.690s	103.975us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	1.020s	24.441us	5	5	100.00
		pwrmgr_csr_rw	0.960s	63.276us	20	20	100.00
		pwrmgr_csr_aliasing	1.120s	142.202us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.170s	23.288us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	1.020s	24.441us	5	5	100.00
		pwrmgr_csr_rw	0.960s	63.276us	20	20	100.00
		pwrmgr_csr_aliasing	1.120s	142.202us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.170s	23.288us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.300s	313.556us	20	20	100.00
		pwrmgr_sec_cm	3.210s	752.844us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	3.210s	752.844us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	3.210s	752.844us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.300s	313.556us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	5.750s	863.739us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	6.910s	858.079us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.590s	67.482us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	1.060s	30.314us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	3.210s	752.844us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	3.210s	752.844us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	3.210s	752.844us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	1.090s	48.383us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	1.120s	54.759us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	2.110s	230.076us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.960s	63.276us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.960s	63.276us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.580s	404.603us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	24.330s	9.549ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.96	98.21	96.58	99.62	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:254) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 38.pwrmgr_disable_rom_integrity_check.98731306251713338035158807197416130716076878631593760307558319355784702574118
      Line 90, in log /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_ERROR @  30650287 ps: (pwrmgr_scoreboard.sv:254) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  30650287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 49.pwrmgr_escalation_timeout.3503722943117576766393955895164177077818188280797878254037606561494467642286
      Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_17/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @ 110246191 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @ 110246191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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