| T329 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.483919982 |
|
|
Feb 09 02:04:39 PM UTC 25 |
Feb 09 02:04:41 PM UTC 25 |
167984467 ps |
| T330 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.826522319 |
|
|
Feb 09 02:04:39 PM UTC 25 |
Feb 09 02:04:42 PM UTC 25 |
205303992 ps |
| T331 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.3367343897 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:44 PM UTC 25 |
37890826 ps |
| T332 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.1551948721 |
|
|
Feb 09 02:04:39 PM UTC 25 |
Feb 09 02:04:44 PM UTC 25 |
935524420 ps |
| T333 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.892359762 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:44 PM UTC 25 |
37158058 ps |
| T334 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2400414496 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:44 PM UTC 25 |
23312491 ps |
| T335 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3195044083 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:44 PM UTC 25 |
50737329 ps |
| T336 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.2101962821 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:44 PM UTC 25 |
37942542 ps |
| T337 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.2613095855 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:45 PM UTC 25 |
100213292 ps |
| T338 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.1623068454 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:45 PM UTC 25 |
53729484 ps |
| T339 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3842700625 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:45 PM UTC 25 |
84585864 ps |
| T340 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.2573480263 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:45 PM UTC 25 |
89631081 ps |
| T341 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.37150356 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:45 PM UTC 25 |
754352746 ps |
| T342 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3577015459 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:46 PM UTC 25 |
1407371422 ps |
| T343 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1034721236 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:47 PM UTC 25 |
869779677 ps |
| T344 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.291975239 |
|
|
Feb 09 02:04:44 PM UTC 25 |
Feb 09 02:04:47 PM UTC 25 |
33361681 ps |
| T345 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.3530730831 |
|
|
Feb 09 02:04:44 PM UTC 25 |
Feb 09 02:04:47 PM UTC 25 |
71674769 ps |
| T346 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.3811999646 |
|
|
Feb 09 02:04:44 PM UTC 25 |
Feb 09 02:04:47 PM UTC 25 |
310029781 ps |
| T347 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2106347887 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:49 PM UTC 25 |
25349968 ps |
| T348 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.3118279937 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
126566997 ps |
| T349 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1033597261 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
31955713 ps |
| T350 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.1620723045 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
33449522 ps |
| T351 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.4114899545 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
101986600 ps |
| T352 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3670696782 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
168770897 ps |
| T353 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.2375139508 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
416602372 ps |
| T354 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.737041100 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
40086296 ps |
| T355 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1846059245 |
|
|
Feb 09 02:04:44 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
1029122492 ps |
| T356 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.2948482501 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
312232627 ps |
| T59 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1493896694 |
|
|
Feb 09 02:04:23 PM UTC 25 |
Feb 09 02:04:50 PM UTC 25 |
6263938922 ps |
| T357 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1475689184 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:51 PM UTC 25 |
1104913524 ps |
| T358 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.1176687581 |
|
|
Feb 09 02:04:49 PM UTC 25 |
Feb 09 02:04:51 PM UTC 25 |
35302112 ps |
| T359 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.347307804 |
|
|
Feb 09 02:04:49 PM UTC 25 |
Feb 09 02:04:52 PM UTC 25 |
43012028 ps |
| T360 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.4151392616 |
|
|
Feb 09 02:04:49 PM UTC 25 |
Feb 09 02:04:52 PM UTC 25 |
48268856 ps |
| T361 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.3917337431 |
|
|
Feb 09 02:04:49 PM UTC 25 |
Feb 09 02:04:52 PM UTC 25 |
108159920 ps |
| T362 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3056146118 |
|
|
Feb 09 02:04:47 PM UTC 25 |
Feb 09 02:04:52 PM UTC 25 |
810185242 ps |
| T363 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3011748941 |
|
|
Feb 09 02:04:50 PM UTC 25 |
Feb 09 02:04:53 PM UTC 25 |
79064199 ps |
| T364 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.3110731248 |
|
|
Feb 09 02:04:50 PM UTC 25 |
Feb 09 02:04:53 PM UTC 25 |
253338914 ps |
| T365 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.2652826206 |
|
|
Feb 09 02:04:49 PM UTC 25 |
Feb 09 02:04:54 PM UTC 25 |
2140578350 ps |
| T366 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1085256096 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
156770803 ps |
| T367 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.1184378481 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:57 PM UTC 25 |
261078322 ps |
| T368 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3802115467 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
40146440 ps |
| T369 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.454703561 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
204908903 ps |
| T370 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.215712055 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
46129420 ps |
| T371 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.548360129 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
34198631 ps |
| T372 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.1126349509 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
156697538 ps |
| T373 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4001804411 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
92424195 ps |
| T189 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.3811602557 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
86426168 ps |
| T374 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3810559476 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:56 PM UTC 25 |
29918472 ps |
| T375 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.551679016 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:57 PM UTC 25 |
43871330 ps |
| T376 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.2011598679 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:57 PM UTC 25 |
601725553 ps |
| T377 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.1592594718 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:57 PM UTC 25 |
95758017 ps |
| T378 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2493515095 |
|
|
Feb 09 02:04:35 PM UTC 25 |
Feb 09 02:04:57 PM UTC 25 |
15033170181 ps |
| T379 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.662140100 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:57 PM UTC 25 |
1138381137 ps |
| T380 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.3110146528 |
|
|
Feb 09 02:04:56 PM UTC 25 |
Feb 09 02:04:58 PM UTC 25 |
43492183 ps |
| T381 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.4258572415 |
|
|
Feb 09 02:04:42 PM UTC 25 |
Feb 09 02:04:58 PM UTC 25 |
5042045658 ps |
| T382 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2160377085 |
|
|
Feb 09 02:04:56 PM UTC 25 |
Feb 09 02:04:58 PM UTC 25 |
220064748 ps |
| T383 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.3718790910 |
|
|
Feb 09 02:04:56 PM UTC 25 |
Feb 09 02:04:58 PM UTC 25 |
403358575 ps |
| T384 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1926672760 |
|
|
Feb 09 02:04:39 PM UTC 25 |
Feb 09 02:04:58 PM UTC 25 |
16719791902 ps |
| T385 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2231778674 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:04:59 PM UTC 25 |
983949646 ps |
| T386 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.660557172 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
31374383 ps |
| T387 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.1487411240 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
56473774 ps |
| T388 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.1030457918 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
45286589 ps |
| T389 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.411470988 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
1643197159 ps |
| T390 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.994524396 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
114374611 ps |
| T391 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1404841174 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
40361891 ps |
| T392 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.2385647054 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
70458111 ps |
| T393 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2557422908 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
72184670 ps |
| T394 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.937638298 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:01 PM UTC 25 |
112869226 ps |
| T395 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.312501009 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:02 PM UTC 25 |
34787130 ps |
| T396 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.3024670157 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:02 PM UTC 25 |
292725317 ps |
| T397 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.470398186 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:02 PM UTC 25 |
328881912 ps |
| T398 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.689923134 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:02 PM UTC 25 |
1279404414 ps |
| T399 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.993877432 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:03 PM UTC 25 |
824082582 ps |
| T400 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.2228453685 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:05 PM UTC 25 |
6804870686 ps |
| T401 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.180120587 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:05 PM UTC 25 |
65969422 ps |
| T402 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2253181345 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
38963703 ps |
| T403 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.215126957 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
70421526 ps |
| T404 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3164374903 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
109539657 ps |
| T405 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.1515260433 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
351693116 ps |
| T406 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.1916839178 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
68553006 ps |
| T407 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.179338992 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
79853462 ps |
| T408 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.257358374 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
69968014 ps |
| T409 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.3830138497 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
41210581 ps |
| T410 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.614618049 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
309382520 ps |
| T411 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3129841121 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
33303865 ps |
| T412 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.2069259516 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
51564754 ps |
| T413 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.2020602353 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
316796409 ps |
| T414 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1771903848 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:06 PM UTC 25 |
76831413 ps |
| T415 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2182624199 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:07 PM UTC 25 |
109636774 ps |
| T416 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2403689510 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:08 PM UTC 25 |
823282264 ps |
| T417 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1113025797 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:08 PM UTC 25 |
785800426 ps |
| T418 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.4052851656 |
|
|
Feb 09 02:05:06 PM UTC 25 |
Feb 09 02:05:08 PM UTC 25 |
32944930 ps |
| T419 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.4291095220 |
|
|
Feb 09 02:05:06 PM UTC 25 |
Feb 09 02:05:08 PM UTC 25 |
46012297 ps |
| T420 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.3928415142 |
|
|
Feb 09 02:05:06 PM UTC 25 |
Feb 09 02:05:09 PM UTC 25 |
370280221 ps |
| T421 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.2246045182 |
|
|
Feb 09 02:05:06 PM UTC 25 |
Feb 09 02:05:09 PM UTC 25 |
296999879 ps |
| T422 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.191942600 |
|
|
Feb 09 02:05:06 PM UTC 25 |
Feb 09 02:05:09 PM UTC 25 |
230870869 ps |
| T423 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.922394227 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:13 PM UTC 25 |
32076778 ps |
| T424 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.2358573805 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:13 PM UTC 25 |
72292706 ps |
| T425 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.2325287652 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:13 PM UTC 25 |
44813831 ps |
| T426 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1626081681 |
|
|
Feb 09 02:04:49 PM UTC 25 |
Feb 09 02:05:13 PM UTC 25 |
10670300420 ps |
| T427 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.454556636 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
33421935 ps |
| T428 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.276899999 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:13 PM UTC 25 |
54530434 ps |
| T429 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.148161837 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
35543926 ps |
| T430 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.2485545503 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
51039470 ps |
| T431 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.4056390338 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
99882153 ps |
| T432 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3079983851 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
112488150 ps |
| T433 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.1706926629 |
|
|
Feb 09 02:05:06 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
1844530497 ps |
| T434 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.685750485 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
116918957 ps |
| T435 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.3757606938 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
576087860 ps |
| T436 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.2437167350 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
52551068 ps |
| T437 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.1520849014 |
|
|
Feb 09 02:05:12 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
180816522 ps |
| T438 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3158032088 |
|
|
Feb 09 02:05:12 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
36786788 ps |
| T439 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.3535803350 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
200805706 ps |
| T440 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.2064649293 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
118202727 ps |
| T441 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.1845262433 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
235130840 ps |
| T442 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3349209177 |
|
|
Feb 09 02:04:54 PM UTC 25 |
Feb 09 02:05:14 PM UTC 25 |
8109732759 ps |
| T443 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2218883489 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:15 PM UTC 25 |
1190795320 ps |
| T444 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2350969955 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:15 PM UTC 25 |
745932512 ps |
| T445 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.173184848 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:16 PM UTC 25 |
559293005 ps |
| T446 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2802747633 |
|
|
Feb 09 02:05:13 PM UTC 25 |
Feb 09 02:05:16 PM UTC 25 |
2209852372 ps |
| T447 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1414456660 |
|
|
Feb 09 02:05:13 PM UTC 25 |
Feb 09 02:05:16 PM UTC 25 |
1363085518 ps |
| T448 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.484884286 |
|
|
Feb 09 02:05:17 PM UTC 25 |
Feb 09 02:05:19 PM UTC 25 |
41124911 ps |
| T449 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.457443410 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:21 PM UTC 25 |
221712715 ps |
| T450 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1724373723 |
|
|
Feb 09 02:05:17 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
271903232 ps |
| T451 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.961536785 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:27 PM UTC 25 |
65166375 ps |
| T452 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.767375637 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
83242556 ps |
| T453 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.2283156640 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
107988505 ps |
| T454 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.2937915623 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
57479286 ps |
| T455 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.36781011 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
57576874 ps |
| T456 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.1198710189 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
66856584 ps |
| T457 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.626852016 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
90135872 ps |
| T458 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2550095050 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
76687244 ps |
| T459 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.1951218323 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
161404460 ps |
| T460 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.3816402705 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
367912310 ps |
| T461 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.3159487380 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
165374974 ps |
| T462 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.949097506 |
|
|
Feb 09 02:05:17 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
72070143 ps |
| T463 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.3670922580 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
90793267 ps |
| T464 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.717280375 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:20 PM UTC 25 |
149179982 ps |
| T465 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.3612854954 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:21 PM UTC 25 |
308373307 ps |
| T466 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2659599177 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:21 PM UTC 25 |
1155609359 ps |
| T467 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.2264480921 |
|
|
Feb 09 02:05:20 PM UTC 25 |
Feb 09 02:05:22 PM UTC 25 |
32772017 ps |
| T468 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.2791085843 |
|
|
Feb 09 02:05:20 PM UTC 25 |
Feb 09 02:05:22 PM UTC 25 |
135635318 ps |
| T469 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.2754291512 |
|
|
Feb 09 02:05:20 PM UTC 25 |
Feb 09 02:05:22 PM UTC 25 |
166292367 ps |
| T470 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3140664716 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:22 PM UTC 25 |
1008429708 ps |
| T471 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.335931673 |
|
|
Feb 09 02:04:59 PM UTC 25 |
Feb 09 02:05:22 PM UTC 25 |
11587511082 ps |
| T84 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.1316708964 |
|
|
Feb 09 02:05:11 PM UTC 25 |
Feb 09 02:05:24 PM UTC 25 |
4635872408 ps |
| T472 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.484688945 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:27 PM UTC 25 |
81976308 ps |
| T473 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3019037778 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
30105431 ps |
| T474 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.3972026753 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:27 PM UTC 25 |
106184698 ps |
| T475 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.2193037688 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
71960183 ps |
| T476 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.3311418878 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:27 PM UTC 25 |
32425982 ps |
| T477 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3354292595 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:27 PM UTC 25 |
104716436 ps |
| T478 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.1151836412 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:27 PM UTC 25 |
59502441 ps |
| T479 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.3383561324 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:40 PM UTC 25 |
43887253 ps |
| T480 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.1366625386 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
68942410 ps |
| T481 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.234619306 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:40 PM UTC 25 |
145510411 ps |
| T482 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3729906214 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
50933686 ps |
| T483 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.2505073584 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
22715511 ps |
| T484 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.2968732391 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
208812453 ps |
| T485 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.578389260 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
38268630 ps |
| T486 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.4159249945 |
|
|
Feb 09 02:05:26 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
73496391 ps |
| T487 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.2452449675 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
318367021 ps |
| T488 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.632727348 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
277140674 ps |
| T489 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.1811622122 |
|
|
Feb 09 02:05:26 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
43855500 ps |
| T490 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3443133568 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
29387330 ps |
| T491 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.1790686983 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
162295803 ps |
| T492 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.3315438737 |
|
|
Feb 09 02:05:26 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
69067274 ps |
| T493 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.3613446045 |
|
|
Feb 09 02:05:26 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
500003104 ps |
| T494 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.145882237 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
263456538 ps |
| T495 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.3170503874 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:28 PM UTC 25 |
1294743096 ps |
| T496 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.426570330 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:29 PM UTC 25 |
909478739 ps |
| T497 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.571305605 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:29 PM UTC 25 |
1316622373 ps |
| T498 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2823841600 |
|
|
Feb 09 02:05:04 PM UTC 25 |
Feb 09 02:05:31 PM UTC 25 |
12034847846 ps |
| T499 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2018636361 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
67561302 ps |
| T500 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.4002006799 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
43993232 ps |
| T501 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.3330422383 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
56994582 ps |
| T502 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3777616749 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
85587601 ps |
| T503 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.4073210254 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
34270966 ps |
| T504 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.376973045 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
47023354 ps |
| T505 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.210664240 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
140564963 ps |
| T506 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2646362059 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:40 PM UTC 25 |
247996813 ps |
| T507 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.736559931 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
38945850 ps |
| T508 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.4114695657 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
30252995 ps |
| T509 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.3813353296 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
111604604 ps |
| T510 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3146786393 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
105830156 ps |
| T511 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.1602478317 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
307911672 ps |
| T512 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.19653641 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:34 PM UTC 25 |
76965587 ps |
| T513 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.2395541292 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
36014877 ps |
| T514 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.4118148037 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
101536805 ps |
| T515 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3637374964 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
43040979 ps |
| T516 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.4232351401 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
66940138 ps |
| T517 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.2181181599 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
161306777 ps |
| T518 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.3971308712 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
2339723135 ps |
| T519 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1765956411 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:35 PM UTC 25 |
110971382 ps |
| T520 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1863198819 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:36 PM UTC 25 |
1104823797 ps |
| T521 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3296345814 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:36 PM UTC 25 |
1274280914 ps |
| T522 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.158903882 |
|
|
Feb 09 02:05:18 PM UTC 25 |
Feb 09 02:05:37 PM UTC 25 |
14956047829 ps |
| T523 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.1662898521 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:38 PM UTC 25 |
2059571711 ps |
| T524 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.4020161662 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
174611863 ps |
| T525 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.4270764806 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
36057856 ps |
| T526 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.3569324191 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
28039365 ps |
| T527 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.2929607939 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
210229378 ps |
| T528 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.3197876362 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
257644591 ps |
| T529 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1833068456 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:39 PM UTC 25 |
122382798 ps |
| T530 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.217983709 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:40 PM UTC 25 |
167874822 ps |
| T531 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2349397844 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:40 PM UTC 25 |
159999407 ps |
| T532 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.513836496 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:40 PM UTC 25 |
1230211096 ps |
| T533 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3769716848 |
|
|
Feb 09 02:05:37 PM UTC 25 |
Feb 09 02:05:41 PM UTC 25 |
1627102881 ps |
| T534 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.3979999784 |
|
|
Feb 09 02:05:25 PM UTC 25 |
Feb 09 02:05:45 PM UTC 25 |
11734682449 ps |
| T535 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.3642124105 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
206971290 ps |
| T536 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2439973804 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
31971932 ps |
| T537 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.170141866 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
144771841 ps |
| T538 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3469635168 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
36768137 ps |
| T539 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.3129207362 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
102539393 ps |
| T540 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.446856235 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
109321021 ps |
| T541 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.507710192 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
53865378 ps |
| T542 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.3947956394 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
64394834 ps |
| T543 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.2183689544 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:46 PM UTC 25 |
55038024 ps |
| T544 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.1032544251 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
835944541 ps |
| T545 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.900985548 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
104265839 ps |
| T546 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.2121628567 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
26280432 ps |
| T547 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.350262488 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
44203276 ps |
| T548 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.3469861055 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
745940441 ps |
| T549 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.576659696 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
115191109 ps |
| T550 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1549626634 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
286989042 ps |
| T551 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3786450386 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:47 PM UTC 25 |
1109441122 ps |
| T552 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.3845601039 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:48 PM UTC 25 |
6067622664 ps |
| T553 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3608764599 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:48 PM UTC 25 |
784193782 ps |
| T554 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.1264378731 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:49 PM UTC 25 |
3891656168 ps |
| T96 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.547221018 |
|
|
Feb 09 02:05:38 PM UTC 25 |
Feb 09 02:05:52 PM UTC 25 |
9730448412 ps |
| T85 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.2178158913 |
|
|
Feb 09 02:05:32 PM UTC 25 |
Feb 09 02:05:53 PM UTC 25 |
14014920298 ps |
| T555 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.1243124837 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
61163325 ps |
| T556 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1480412600 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
32852280 ps |
| T557 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.3864845872 |
|
|
Feb 09 02:05:51 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
52975222 ps |
| T558 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.1228488885 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
69202756 ps |
| T559 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.3855259938 |
|
|
Feb 09 02:05:51 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
124612572 ps |
| T560 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.445952683 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
92578233 ps |
| T561 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.341406494 |
|
|
Feb 09 02:05:51 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
119315831 ps |
| T562 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.2933040874 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
131594088 ps |
| T190 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.953714505 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
60846204 ps |
| T563 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.93956162 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
57434524 ps |
| T564 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.369865100 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
76181102 ps |
| T565 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.978464917 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
52278829 ps |
| T566 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.3772163245 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
88967249 ps |
| T567 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.2426979174 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
70701470 ps |
| T568 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.2178527639 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
168730667 ps |
| T569 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.4276627579 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:54 PM UTC 25 |
101163609 ps |
| T570 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.3193303550 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:55 PM UTC 25 |
272848221 ps |
| T571 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3852457153 |
|
|
Feb 09 02:05:51 PM UTC 25 |
Feb 09 02:05:55 PM UTC 25 |
810047835 ps |
| T572 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.3192444000 |
|
|
Feb 09 02:05:44 PM UTC 25 |
Feb 09 02:05:55 PM UTC 25 |
7832176753 ps |