| T573 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3613499816 |
|
|
Feb 09 02:05:51 PM UTC 25 |
Feb 09 02:05:56 PM UTC 25 |
978045259 ps |
| T574 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.1054467572 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:05:57 PM UTC 25 |
724595234 ps |
| T575 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.2601626540 |
|
|
Feb 09 02:05:52 PM UTC 25 |
Feb 09 02:06:00 PM UTC 25 |
4534046195 ps |
| T576 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.250428732 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
59200116 ps |
| T577 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.915700908 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
29829467 ps |
| T578 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.260094198 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
33523798 ps |
| T579 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2959107895 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
50282720 ps |
| T580 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2274859515 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
65060458 ps |
| T581 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.2950678079 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
75438463 ps |
| T582 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.382090624 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
63873595 ps |
| T583 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.2061457919 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
43794912 ps |
| T584 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.498671208 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
209480641 ps |
| T585 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.56624303 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
56935490 ps |
| T586 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.723214883 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:01 PM UTC 25 |
38418745 ps |
| T587 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.64211863 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:02 PM UTC 25 |
891049198 ps |
| T588 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.1447292839 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:02 PM UTC 25 |
40766615 ps |
| T589 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.2928617718 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:02 PM UTC 25 |
441252276 ps |
| T590 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.2437566103 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:02 PM UTC 25 |
98324262 ps |
| T591 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.3680604016 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:02 PM UTC 25 |
373471501 ps |
| T592 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.141877348 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:03 PM UTC 25 |
896056626 ps |
| T593 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2762911107 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:03 PM UTC 25 |
889726671 ps |
| T594 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.2889509996 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:03 PM UTC 25 |
2026448650 ps |
| T595 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1143718826 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:04 PM UTC 25 |
830412480 ps |
| T596 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2417867315 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:04 PM UTC 25 |
899542681 ps |
| T597 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.3313086265 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
37809376 ps |
| T598 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3005365869 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
77091804 ps |
| T599 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.1934619051 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
22849922 ps |
| T600 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.3088212778 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
33871763 ps |
| T191 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2036951578 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
90322319 ps |
| T601 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.1701804897 |
|
|
Feb 09 02:06:29 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
71504320 ps |
| T602 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1390175888 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
292508740 ps |
| T603 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.2624157735 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
71562594 ps |
| T604 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.2905888346 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:09 PM UTC 25 |
164059687 ps |
| T605 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.2214324237 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
31420828 ps |
| T606 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.1749838015 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
129454000 ps |
| T607 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3147286264 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
44865836 ps |
| T608 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.3133711885 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
67245265 ps |
| T609 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.547736353 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
124494562 ps |
| T610 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3081663023 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
46180739 ps |
| T611 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.4156743930 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
89889055 ps |
| T612 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2543475865 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
33423198 ps |
| T613 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.2280358828 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
80505175 ps |
| T614 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.635796007 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
130925777 ps |
| T615 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3251268419 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
95915496 ps |
| T616 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.4033070365 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
153573786 ps |
| T617 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.557530108 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:10 PM UTC 25 |
319745525 ps |
| T618 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.3063793286 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:11 PM UTC 25 |
321282168 ps |
| T619 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4162838085 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:11 PM UTC 25 |
1090089055 ps |
| T620 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.2317674328 |
|
|
Feb 09 02:06:10 PM UTC 25 |
Feb 09 02:06:12 PM UTC 25 |
62063124 ps |
| T621 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.1035039415 |
|
|
Feb 09 02:06:10 PM UTC 25 |
Feb 09 02:06:12 PM UTC 25 |
162080898 ps |
| T622 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.1046663613 |
|
|
Feb 09 02:06:10 PM UTC 25 |
Feb 09 02:06:12 PM UTC 25 |
67641010 ps |
| T623 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1804520263 |
|
|
Feb 09 02:06:08 PM UTC 25 |
Feb 09 02:06:12 PM UTC 25 |
848755766 ps |
| T624 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.2101124037 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:12 PM UTC 25 |
2109950942 ps |
| T625 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.2940300133 |
|
|
Feb 09 02:06:07 PM UTC 25 |
Feb 09 02:06:15 PM UTC 25 |
9551584723 ps |
| T626 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.2891999906 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
61667326 ps |
| T627 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.4161451078 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
90667846 ps |
| T628 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.929851794 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
50806478 ps |
| T629 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.2735253114 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
174180564 ps |
| T630 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.3746103683 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
193653474 ps |
| T631 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2258634016 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
325199108 ps |
| T632 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.1672277000 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
151666623 ps |
| T633 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.166626715 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
162562622 ps |
| T634 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.2753246170 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
62705543 ps |
| T635 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3846226494 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
37800206 ps |
| T636 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.3362036460 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
35834953 ps |
| T637 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.684682293 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
175034746 ps |
| T638 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.3009292778 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
29527882 ps |
| T639 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.2908118988 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
30035664 ps |
| T640 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3591211766 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:20 PM UTC 25 |
407498041 ps |
| T641 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.810686610 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
75933470 ps |
| T642 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.3567715632 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
150123317 ps |
| T643 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.650117389 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
54413758 ps |
| T644 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2112510777 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
31200275 ps |
| T645 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.1336455486 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
230165114 ps |
| T646 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.235916861 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
29464427 ps |
| T647 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.3918303465 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
629491640 ps |
| T648 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2361362857 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
162905904 ps |
| T649 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.3868860368 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
376289390 ps |
| T650 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.4154431619 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
298604009 ps |
| T651 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.2000788740 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
180953058 ps |
| T652 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.3513326206 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:21 PM UTC 25 |
529102596 ps |
| T653 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.2800525185 |
|
|
Feb 09 02:06:20 PM UTC 25 |
Feb 09 02:06:22 PM UTC 25 |
41825475 ps |
| T654 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4122692029 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:22 PM UTC 25 |
993014168 ps |
| T655 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.778712344 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:22 PM UTC 25 |
931971213 ps |
| T656 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3515825810 |
|
|
Feb 09 02:05:59 PM UTC 25 |
Feb 09 02:06:23 PM UTC 25 |
7676472286 ps |
| T657 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.2868778299 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
63122986 ps |
| T658 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.3325534895 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
64496580 ps |
| T659 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.2896925268 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
48655741 ps |
| T660 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4125549146 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
67440956 ps |
| T661 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.3116569996 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
54862392 ps |
| T662 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1209915770 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
30152644 ps |
| T186 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.4102155260 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
63691484 ps |
| T663 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.3480804229 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
86830260 ps |
| T664 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.452703135 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:30 PM UTC 25 |
348218997 ps |
| T665 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.1957476171 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
29034540 ps |
| T666 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3306386802 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
33187024 ps |
| T667 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3218049111 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
53559161 ps |
| T668 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.303500423 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
449628096 ps |
| T669 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2968125002 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
2907377296 ps |
| T670 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.1467398156 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
311683086 ps |
| T671 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3364068443 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
1045834109 ps |
| T672 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1671646421 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:31 PM UTC 25 |
212500976 ps |
| T673 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.1523481736 |
|
|
Feb 09 02:06:30 PM UTC 25 |
Feb 09 02:06:32 PM UTC 25 |
69845128 ps |
| T674 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.536934431 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:32 PM UTC 25 |
764114552 ps |
| T675 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2560651143 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:34 PM UTC 25 |
900405232 ps |
| T97 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.3818534179 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:06:35 PM UTC 25 |
17127304136 ps |
| T676 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.991389235 |
|
|
Feb 09 02:06:28 PM UTC 25 |
Feb 09 02:06:39 PM UTC 25 |
4109002812 ps |
| T677 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.439879165 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
69322443 ps |
| T678 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.1543784426 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
43032585 ps |
| T679 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3150879784 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
95906828 ps |
| T680 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.795929242 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
29360010 ps |
| T681 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.460619247 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
27532718 ps |
| T682 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1326195446 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
51900602 ps |
| T683 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.272025952 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
121439082 ps |
| T684 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.944285575 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
56057633 ps |
| T685 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.3779416548 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
31321867 ps |
| T686 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.2476604510 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
110402701 ps |
| T687 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.1951542968 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:40 PM UTC 25 |
286420686 ps |
| T688 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.2329354082 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
103899500 ps |
| T689 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.4185663993 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
135886307 ps |
| T690 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.3936969593 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
31700635 ps |
| T691 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.1919391498 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
268064365 ps |
| T692 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2617096464 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
69394781 ps |
| T693 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.2258764216 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
638403185 ps |
| T694 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.295359321 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
224241521 ps |
| T695 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.2470975033 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:41 PM UTC 25 |
224007306 ps |
| T696 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.3615993398 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:42 PM UTC 25 |
256149270 ps |
| T697 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.1271343855 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:42 PM UTC 25 |
1437035344 ps |
| T698 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3163694557 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:42 PM UTC 25 |
961312630 ps |
| T699 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4007460130 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:43 PM UTC 25 |
913234955 ps |
| T700 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3863911834 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:06:46 PM UTC 25 |
9064885771 ps |
| T701 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.60484952 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
94323984 ps |
| T702 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.4264107820 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
100661106 ps |
| T703 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2151235801 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
32726125 ps |
| T704 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2530693159 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
70971336 ps |
| T705 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.2199071742 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
298405866 ps |
| T706 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.557259858 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
132948717 ps |
| T707 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.2958255368 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
49569126 ps |
| T708 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.2487272250 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
62115187 ps |
| T709 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.2398569652 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
55049495 ps |
| T710 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.415467526 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
61322979 ps |
| T711 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.756823512 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:49 PM UTC 25 |
634997573 ps |
| T712 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.2082079022 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
29231172 ps |
| T713 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2042243430 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
117421056 ps |
| T714 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.1629005132 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
163228182 ps |
| T715 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.3250188572 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
53983660 ps |
| T716 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.3311217214 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
192479106 ps |
| T717 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.1895958820 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
130248742 ps |
| T718 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.1800314187 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
180579863 ps |
| T719 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.1804425922 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
44690654 ps |
| T720 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.97848998 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
69352077 ps |
| T721 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1232758771 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:50 PM UTC 25 |
891281582 ps |
| T722 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1789919429 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:51 PM UTC 25 |
1020505287 ps |
| T723 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.76170152 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:51 PM UTC 25 |
1413440397 ps |
| T724 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.526551506 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:51 PM UTC 25 |
848329397 ps |
| T725 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3527932183 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:06:51 PM UTC 25 |
845584773 ps |
| T726 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1762532248 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
75386775 ps |
| T727 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.4035529924 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
25469789 ps |
| T728 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3179369503 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
64706535 ps |
| T729 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.798069226 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
51176630 ps |
| T730 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.2776966437 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
26426463 ps |
| T731 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2536531509 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
56875431 ps |
| T732 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.903765118 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
115787351 ps |
| T733 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.753364533 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
159535175 ps |
| T734 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.1485189134 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
42283510 ps |
| T735 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.291517465 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
55452948 ps |
| T736 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.217231046 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
84234582 ps |
| T737 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.2120710335 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
67994510 ps |
| T738 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.4161556758 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
152343229 ps |
| T739 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.3711747450 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
24280672 ps |
| T740 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.2381013790 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:58 PM UTC 25 |
88531554 ps |
| T741 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1316010449 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
28609993 ps |
| T742 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.1277938272 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
104000233 ps |
| T743 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.148934583 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
89686902 ps |
| T744 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.4163594963 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
355706227 ps |
| T745 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.358047241 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
64831538 ps |
| T746 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.35670312 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
328487800 ps |
| T747 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.922334993 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
317165074 ps |
| T748 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3336203979 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:06:59 PM UTC 25 |
1716557217 ps |
| T749 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.141989802 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:07:00 PM UTC 25 |
1032612281 ps |
| T750 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3080946448 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:07:00 PM UTC 25 |
1086010657 ps |
| T74 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.1681154576 |
|
|
Feb 09 02:06:18 PM UTC 25 |
Feb 09 02:07:00 PM UTC 25 |
10974053541 ps |
| T751 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.2291739452 |
|
|
Feb 09 02:06:47 PM UTC 25 |
Feb 09 02:07:02 PM UTC 25 |
9570228738 ps |
| T752 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.2941023439 |
|
|
Feb 09 02:07:03 PM UTC 25 |
Feb 09 02:07:05 PM UTC 25 |
73054248 ps |
| T753 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.545493352 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
35535687 ps |
| T754 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.3425814639 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
115414596 ps |
| T755 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.2595471028 |
|
|
Feb 09 02:07:03 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
107300793 ps |
| T756 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.659402498 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
28655057 ps |
| T757 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1206337821 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
25689433 ps |
| T758 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3770543809 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
53558744 ps |
| T759 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2114468465 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
233647604 ps |
| T760 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.458200301 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
40165237 ps |
| T761 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2187362090 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
39590138 ps |
| T762 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.2440640313 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
130472821 ps |
| T763 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2753922651 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
62397526 ps |
| T764 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.2254945681 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
42192154 ps |
| T765 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.2569794440 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
47212780 ps |
| T766 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.741163318 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
309956730 ps |
| T767 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.1766022277 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
309449387 ps |
| T768 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.1284353202 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:06 PM UTC 25 |
459635937 ps |
| T769 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.988233979 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:07 PM UTC 25 |
108937227 ps |
| T770 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1541137213 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:07 PM UTC 25 |
1114611306 ps |
| T771 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.365615281 |
|
|
Feb 09 02:06:38 PM UTC 25 |
Feb 09 02:07:07 PM UTC 25 |
8098998065 ps |
| T772 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3496968815 |
|
|
Feb 09 02:07:03 PM UTC 25 |
Feb 09 02:07:07 PM UTC 25 |
1513224151 ps |
| T773 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3630887594 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:08 PM UTC 25 |
838226609 ps |
| T774 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1098864152 |
|
|
Feb 09 02:06:56 PM UTC 25 |
Feb 09 02:07:10 PM UTC 25 |
27091860590 ps |
| T142 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3798121003 |
|
|
Feb 09 02:07:03 PM UTC 25 |
Feb 09 02:07:15 PM UTC 25 |
5592539453 ps |
| T147 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.1181838508 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:15 PM UTC 25 |
29789126 ps |
| T148 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.3589136730 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
61927254 ps |
| T149 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.1436219426 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
234370841 ps |
| T150 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.224225650 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
61090861 ps |
| T151 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.1733746968 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
344148660 ps |
| T152 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.777332498 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
30139510 ps |
| T153 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3879530315 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
22561022 ps |
| T154 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.3324913422 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
152560693 ps |
| T155 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.4159124771 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
304872379 ps |
| T775 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.3068481250 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
1084691886 ps |
| T776 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.296673916 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
42716848 ps |
| T777 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1740568020 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
88846812 ps |
| T778 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.1853180850 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
273085882 ps |
| T779 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.4028192572 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
60670371 ps |
| T780 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.4008376276 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
39548755 ps |
| T781 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.3856559639 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
128674319 ps |
| T782 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.1059340669 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:16 PM UTC 25 |
67916063 ps |
| T783 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.676117327 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:17 PM UTC 25 |
218814187 ps |
| T784 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.2270495937 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:17 PM UTC 25 |
80220426 ps |
| T785 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.367920111 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:17 PM UTC 25 |
194361315 ps |
| T786 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2723684831 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:17 PM UTC 25 |
2974451435 ps |
| T787 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.4205938255 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:17 PM UTC 25 |
279668159 ps |
| T788 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2749901362 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:18 PM UTC 25 |
1243547678 ps |
| T789 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3871448892 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:19 PM UTC 25 |
796356624 ps |
| T790 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.2410044556 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:19 PM UTC 25 |
2125075279 ps |
| T791 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2078816814 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:19 PM UTC 25 |
865904294 ps |
| T792 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.3412053054 |
|
|
Feb 09 02:07:04 PM UTC 25 |
Feb 09 02:07:19 PM UTC 25 |
26165949794 ps |
| T793 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2261940964 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
38582673 ps |
| T794 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.2731823359 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
40458737 ps |
| T795 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.4032290458 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
75041629 ps |
| T796 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.1141558640 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
47790510 ps |
| T797 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.1025354612 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
52889733 ps |
| T798 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174305598 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
108527338 ps |
| T799 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.995262342 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
394137631 ps |
| T800 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.2470319369 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
71257500 ps |
| T801 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.899723074 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
154765331 ps |
| T802 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3219129396 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:27 PM UTC 25 |
143204390 ps |
| T803 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1529113571 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
605784600 ps |
| T804 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.2544390303 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
44548738 ps |
| T805 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.900549864 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
29300739 ps |
| T806 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.2020035249 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
41818322 ps |
| T807 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4207666586 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
31963683 ps |
| T808 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.2602140456 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
260602302 ps |