| T809 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.2549484726 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
35374726 ps |
| T810 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2503888503 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
286984613 ps |
| T811 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.970261276 |
|
|
Feb 09 02:07:26 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
70077126 ps |
| T812 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2548429297 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
28041430 ps |
| T813 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1774704858 |
|
|
Feb 09 02:07:26 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
182768676 ps |
| T814 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.987747977 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
824157535 ps |
| T815 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.1016314638 |
|
|
Feb 09 02:07:26 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
52348711 ps |
| T816 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2719125192 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
54040768 ps |
| T817 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.1368145858 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:28 PM UTC 25 |
160575675 ps |
| T818 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3553750990 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:29 PM UTC 25 |
1242607752 ps |
| T819 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379002443 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:30 PM UTC 25 |
827626216 ps |
| T156 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1658223685 |
|
|
Feb 09 02:07:25 PM UTC 25 |
Feb 09 02:07:34 PM UTC 25 |
1952369425 ps |
| T820 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3312981059 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:38 PM UTC 25 |
36221006 ps |
| T821 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.232782350 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:38 PM UTC 25 |
45755479 ps |
| T822 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.2844732384 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:38 PM UTC 25 |
32048561 ps |
| T823 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.1818411884 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:38 PM UTC 25 |
29221977 ps |
| T824 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.995594805 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
52558123 ps |
| T825 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.700344829 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
38658031 ps |
| T826 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.4147600844 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
190194495 ps |
| T827 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.4086588146 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
106135746 ps |
| T828 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.779536181 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
131632621 ps |
| T829 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.701161578 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
51090902 ps |
| T830 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1131300252 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
77266842 ps |
| T831 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.3693468268 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
81775613 ps |
| T832 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.2241866677 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
58196740 ps |
| T833 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.3032791615 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
157998718 ps |
| T834 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2249619909 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
103467277 ps |
| T835 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.1308692754 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
179209357 ps |
| T836 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.1878295738 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
258894591 ps |
| T837 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.1898740546 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
30910621 ps |
| T838 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.2745410604 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:39 PM UTC 25 |
208619144 ps |
| T839 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.861334368 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:40 PM UTC 25 |
118833284 ps |
| T840 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.3483325303 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:40 PM UTC 25 |
64703291 ps |
| T841 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4200333590 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:40 PM UTC 25 |
1045485685 ps |
| T842 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3627770980 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:40 PM UTC 25 |
1168373490 ps |
| T843 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2239293417 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:41 PM UTC 25 |
927457279 ps |
| T844 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.654166829 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:42 PM UTC 25 |
1135727091 ps |
| T845 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.2881352483 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:42 PM UTC 25 |
1395796749 ps |
| T846 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4098431748 |
|
|
Feb 09 02:07:14 PM UTC 25 |
Feb 09 02:07:47 PM UTC 25 |
9686200427 ps |
| T847 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.2329693935 |
|
|
Feb 09 02:07:36 PM UTC 25 |
Feb 09 02:07:49 PM UTC 25 |
3750835440 ps |
| T848 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2949459422 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
69034137 ps |
| T75 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.4226075390 |
|
|
Feb 09 02:07:37 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
7218624703 ps |
| T849 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.3850110823 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
72444592 ps |
| T850 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2851578805 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
57855802 ps |
| T851 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.523980371 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
151067878 ps |
| T852 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.357247509 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
98914690 ps |
| T853 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2235595756 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
237985905 ps |
| T854 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2559811524 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
80831143 ps |
| T855 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4054041187 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
68035302 ps |
| T856 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2990345073 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
117242073 ps |
| T857 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.2107811978 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
77106695 ps |
| T858 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1887579397 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
117069750 ps |
| T859 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.68190690 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
54089052 ps |
| T860 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3309646640 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
159884185 ps |
| T861 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.3220818989 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:50 PM UTC 25 |
39952204 ps |
| T862 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.598584644 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
18619131 ps |
| T863 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.4030744834 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
86846892 ps |
| T864 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.979082146 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
163066788 ps |
| T865 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4175618096 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
101119980 ps |
| T866 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.3684803994 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
49134202 ps |
| T867 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.4112904130 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
36090965 ps |
| T868 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.2335037043 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
799262468 ps |
| T869 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2126838538 |
|
|
Feb 09 02:07:47 PM UTC 25 |
Feb 09 02:07:51 PM UTC 25 |
1401095658 ps |
| T870 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2416511290 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:52 PM UTC 25 |
2047675023 ps |
| T871 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1300846378 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:52 PM UTC 25 |
1052609155 ps |
| T872 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.2048313388 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:07:53 PM UTC 25 |
1748693383 ps |
| T873 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1729571157 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:02 PM UTC 25 |
163354465 ps |
| T874 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.426317559 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
32630611 ps |
| T875 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.2930638929 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:02 PM UTC 25 |
55784892 ps |
| T876 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2815336728 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:02 PM UTC 25 |
20521965 ps |
| T877 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.1624783920 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
82714442 ps |
| T878 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.3305466378 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
109264162 ps |
| T879 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.2948972255 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
150191447 ps |
| T880 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3766756074 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
65193458 ps |
| T881 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.769167978 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
166271080 ps |
| T882 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.3094610417 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
38606398 ps |
| T883 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.2264957300 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
470947389 ps |
| T884 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4241488791 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
79019773 ps |
| T885 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.3653043989 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
103953865 ps |
| T886 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3968326695 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
39496228 ps |
| T887 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1725706282 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
83831095 ps |
| T888 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.74480096 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
161129232 ps |
| T889 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.2455039445 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
99332584 ps |
| T890 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2227607633 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
302182472 ps |
| T891 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.977617212 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
47543439 ps |
| T892 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3738119854 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:03 PM UTC 25 |
35984506 ps |
| T893 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.444016592 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
42261618 ps |
| T894 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.3159272747 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
217463775 ps |
| T895 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3126197578 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
276235383 ps |
| T896 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.2431456175 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
103457464 ps |
| T897 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.1460332491 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
334085901 ps |
| T898 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.481314222 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
1156353020 ps |
| T899 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1752343592 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:04 PM UTC 25 |
269601690 ps |
| T900 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2363620234 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:05 PM UTC 25 |
869792301 ps |
| T901 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.2620169777 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:06 PM UTC 25 |
1073526275 ps |
| T902 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2649422256 |
|
|
Feb 09 02:08:02 PM UTC 25 |
Feb 09 02:08:06 PM UTC 25 |
797575635 ps |
| T903 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.2717874593 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:15 PM UTC 25 |
224527947 ps |
| T904 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1644053243 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:15 PM UTC 25 |
31463218 ps |
| T905 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.2463150759 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:15 PM UTC 25 |
138705392 ps |
| T906 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.3087049072 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
76712937 ps |
| T907 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.578058585 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
89280219 ps |
| T908 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.627392040 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
307478590 ps |
| T909 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.797410387 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
55117263 ps |
| T910 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.1703063180 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
190657052 ps |
| T911 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.2543218979 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
50596515 ps |
| T912 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.371211787 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
62565742 ps |
| T913 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1343802376 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
55326460 ps |
| T914 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.621847374 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
154751026 ps |
| T915 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.4123895275 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
237643564 ps |
| T916 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3793805143 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
109991922 ps |
| T917 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1632852457 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
259434958 ps |
| T143 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.3175397022 |
|
|
Feb 09 02:07:48 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
8070399913 ps |
| T918 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.1215744012 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
82954383 ps |
| T919 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2832605891 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
481769224 ps |
| T920 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.2810640333 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
61994420 ps |
| T921 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.3885265616 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
52737198 ps |
| T922 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.1683181886 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
161282395 ps |
| T923 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.79638156 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:16 PM UTC 25 |
164461537 ps |
| T924 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.2135524152 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:17 PM UTC 25 |
371263017 ps |
| T925 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1474221284 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:17 PM UTC 25 |
101918642 ps |
| T926 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.1536238058 |
|
|
Feb 09 02:08:15 PM UTC 25 |
Feb 09 02:08:17 PM UTC 25 |
82786650 ps |
| T927 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3116836857 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:17 PM UTC 25 |
1162405920 ps |
| T928 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3358250035 |
|
|
Feb 09 02:08:14 PM UTC 25 |
Feb 09 02:08:18 PM UTC 25 |
815316243 ps |
| T929 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590009698 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:18 PM UTC 25 |
889706375 ps |
| T930 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2124743657 |
|
|
Feb 09 02:08:00 PM UTC 25 |
Feb 09 02:08:19 PM UTC 25 |
9516665854 ps |
| T931 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.284457331 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:22 PM UTC 25 |
2056834514 ps |
| T932 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.972482684 |
|
|
Feb 09 02:08:13 PM UTC 25 |
Feb 09 02:08:23 PM UTC 25 |
3341114701 ps |
| T933 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2240807342 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
57071653 ps |
| T934 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3879548312 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
48960209 ps |
| T935 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3451429033 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
30509876 ps |
| T936 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.2097123430 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
90164090 ps |
| T937 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3901940498 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
95645914 ps |
| T938 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.374424504 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
45196996 ps |
| T939 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.3277515349 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:28 PM UTC 25 |
44775080 ps |
| T940 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.1255216709 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
96482123 ps |
| T941 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.3518223885 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
89255379 ps |
| T942 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.316902544 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
95965279 ps |
| T943 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.741734247 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
25861472 ps |
| T944 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.3264443539 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
317039901 ps |
| T945 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.4128533538 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
180104502 ps |
| T946 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.2933102324 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
306952159 ps |
| T947 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1058788557 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
117124699 ps |
| T948 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2247172452 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
99967114 ps |
| T949 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.82668258 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
193696039 ps |
| T950 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2041365700 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:29 PM UTC 25 |
245014791 ps |
| T951 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2837625114 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:30 PM UTC 25 |
1034878163 ps |
| T144 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.534411446 |
|
|
Feb 09 02:08:01 PM UTC 25 |
Feb 09 02:08:30 PM UTC 25 |
8940445283 ps |
| T952 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89987866 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:30 PM UTC 25 |
1545976768 ps |
| T953 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.4008536494 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:31 PM UTC 25 |
468261298 ps |
| T954 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.1277561818 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:31 PM UTC 25 |
1558753017 ps |
| T955 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.4145374045 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
53745080 ps |
| T956 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1504066912 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
65287707 ps |
| T957 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3593142592 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
31096993 ps |
| T958 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.4016989944 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
34982153 ps |
| T187 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1122356734 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
62516822 ps |
| T959 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.3081649969 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
98242530 ps |
| T960 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.2003480391 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
41502447 ps |
| T145 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.250909178 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:09:04 PM UTC 25 |
11951581593 ps |
| T961 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.72308181 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
45298819 ps |
| T962 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.2725393242 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
562404416 ps |
| T963 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3801454362 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
45628945 ps |
| T964 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.3128536727 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
121117149 ps |
| T965 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.2571090588 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:41 PM UTC 25 |
36647666 ps |
| T966 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.286870231 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
142464879 ps |
| T967 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.4250355527 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
46848983 ps |
| T968 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.115201587 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
37072275 ps |
| T969 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.247475980 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
164970724 ps |
| T970 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3722231310 |
|
|
Feb 09 02:08:40 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
46629599 ps |
| T971 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.1385015232 |
|
|
Feb 09 02:08:40 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
66341645 ps |
| T972 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.974710399 |
|
|
Feb 09 02:08:40 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
49972496 ps |
| T973 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.2064494895 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
329979765 ps |
| T974 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.3568007295 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
136121510 ps |
| T975 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.3175843682 |
|
|
Feb 09 02:08:40 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
165484678 ps |
| T976 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.871167435 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:42 PM UTC 25 |
1263130505 ps |
| T977 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2553042426 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:43 PM UTC 25 |
1239721197 ps |
| T978 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163844603 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:43 PM UTC 25 |
839693842 ps |
| T979 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815348778 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:43 PM UTC 25 |
872627433 ps |
| T980 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.671929291 |
|
|
Feb 09 02:08:39 PM UTC 25 |
Feb 09 02:08:44 PM UTC 25 |
2325495285 ps |
| T65 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2417367642 |
|
|
Feb 09 02:08:26 PM UTC 25 |
Feb 09 02:08:46 PM UTC 25 |
8698448376 ps |
| T86 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4139430612 |
|
|
Feb 09 02:08:27 PM UTC 25 |
Feb 09 02:08:52 PM UTC 25 |
11642144227 ps |
| T981 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.451047688 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
55266623 ps |
| T188 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.206756009 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
55515095 ps |
| T982 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.4279935334 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
36279790 ps |
| T983 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.2337763942 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
84997968 ps |
| T984 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.841462299 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
32387240 ps |
| T985 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.2162118958 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
38603886 ps |
| T986 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2521475743 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
38243538 ps |
| T987 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.878868250 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
45329970 ps |
| T988 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.3726534475 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
103147407 ps |
| T989 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.2625180769 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
77522509 ps |
| T990 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.3960267037 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
74188478 ps |
| T991 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2546326381 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
65152140 ps |
| T992 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1967280708 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
97864655 ps |
| T993 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.3868798915 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:54 PM UTC 25 |
56809609 ps |
| T994 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.479252256 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:55 PM UTC 25 |
295177917 ps |
| T995 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2498988200 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:55 PM UTC 25 |
389781316 ps |
| T996 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.2222805349 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:55 PM UTC 25 |
108504068 ps |
| T997 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.4202323287 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:55 PM UTC 25 |
323761273 ps |
| T998 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.966144474 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:55 PM UTC 25 |
714185758 ps |
| T999 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1125619826 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:56 PM UTC 25 |
1030718224 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3254319926 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:56 PM UTC 25 |
890533180 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1399704833 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:08:59 PM UTC 25 |
1544734566 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.2697724591 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:09:01 PM UTC 25 |
3035158544 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.425367952 |
|
|
Feb 09 02:08:52 PM UTC 25 |
Feb 09 02:09:02 PM UTC 25 |
13503244457 ps |
| T52 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2885248141 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:40 AM UTC 25 |
41025330 ps |
| T55 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.3327182573 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:40 AM UTC 25 |
29174038 ps |
| T53 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3632372615 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:40 AM UTC 25 |
27660449 ps |
| T54 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.462882686 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:40 AM UTC 25 |
20499680 ps |
| T56 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1071944306 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:40 AM UTC 25 |
27174828 ps |
| T62 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2727780035 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:40 AM UTC 25 |
115056774 ps |
| T47 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4021461716 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:41 AM UTC 25 |
185067611 ps |
| T63 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3513931804 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:41 AM UTC 25 |
464179365 ps |
| T48 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1738363186 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:41 AM UTC 25 |
84759431 ps |
| T57 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.504057679 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:41 AM UTC 25 |
156312629 ps |
| T183 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3346109123 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:41 AM UTC 25 |
131919112 ps |
| T51 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.320155180 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:42 AM UTC 25 |
146395694 ps |
| T66 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.592512922 |
|
|
Feb 09 08:32:38 AM UTC 25 |
Feb 09 08:32:42 AM UTC 25 |
192640532 ps |
| T113 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1911303951 |
|
|
Feb 09 08:32:40 AM UTC 25 |
Feb 09 08:32:42 AM UTC 25 |
57014713 ps |
| T182 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1782613000 |
|
|
Feb 09 08:32:40 AM UTC 25 |
Feb 09 08:32:42 AM UTC 25 |
78423049 ps |
| T178 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2909671775 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:44 AM UTC 25 |
23669965 ps |
| T146 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1405764395 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:44 AM UTC 25 |
60779100 ps |
| T123 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.3975537135 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:44 AM UTC 25 |
16827428 ps |
| T124 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2218256181 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:44 AM UTC 25 |
36714578 ps |
| T184 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.868068250 |
|
|
Feb 09 08:32:40 AM UTC 25 |
Feb 09 08:32:45 AM UTC 25 |
268242606 ps |
| T77 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.529244003 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:45 AM UTC 25 |
53876965 ps |
| T125 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1842251601 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:45 AM UTC 25 |
45252357 ps |
| T73 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1922180718 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:45 AM UTC 25 |
75466349 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.695185686 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:45 AM UTC 25 |
151481756 ps |
| T180 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1918591669 |
|
|
Feb 09 08:32:44 AM UTC 25 |
Feb 09 08:32:46 AM UTC 25 |
46286940 ps |
| T1005 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.943113994 |
|
|
Feb 09 08:32:44 AM UTC 25 |
Feb 09 08:32:46 AM UTC 25 |
43637969 ps |
| T71 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3656020522 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:46 AM UTC 25 |
425418753 ps |
| T114 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.535163161 |
|
|
Feb 09 08:32:44 AM UTC 25 |
Feb 09 08:32:46 AM UTC 25 |
44982035 ps |
| T58 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.543799887 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:46 AM UTC 25 |
499695377 ps |
| T1006 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3793869915 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:46 AM UTC 25 |
167344325 ps |
| T76 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.316024620 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:47 AM UTC 25 |
195774026 ps |
| T67 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.1735943805 |
|
|
Feb 09 08:32:42 AM UTC 25 |
Feb 09 08:32:47 AM UTC 25 |
223050136 ps |
| T1007 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1423936259 |
|
|
Feb 09 08:32:45 AM UTC 25 |
Feb 09 08:32:47 AM UTC 25 |
83164198 ps |
| T126 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2022801213 |
|
|
Feb 09 08:32:46 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
29886650 ps |
| T121 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4216984996 |
|
|
Feb 09 08:32:45 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
43464023 ps |
| T179 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.2335477736 |
|
|
Feb 09 08:32:46 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
45407407 ps |
| T1008 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1665097743 |
|
|
Feb 09 08:32:46 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
56821411 ps |
| T1009 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4050411281 |
|
|
Feb 09 08:32:46 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
52171353 ps |
| T1010 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.687661837 |
|
|
Feb 09 08:32:46 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
22736950 ps |
| T1011 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.441624766 |
|
|
Feb 09 08:32:46 AM UTC 25 |
Feb 09 08:32:48 AM UTC 25 |
198997279 ps |
| T115 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3434181594 |
|
|
Feb 09 08:32:47 AM UTC 25 |
Feb 09 08:32:49 AM UTC 25 |
21008568 ps |
| T72 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3644555858 |
|
|
Feb 09 08:32:47 AM UTC 25 |
Feb 09 08:32:49 AM UTC 25 |
67091398 ps |
| T127 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2385673080 |
|
|
Feb 09 08:32:47 AM UTC 25 |
Feb 09 08:32:49 AM UTC 25 |
55432240 ps |
| T1012 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.144634057 |
|
|
Feb 09 08:32:47 AM UTC 25 |
Feb 09 08:32:50 AM UTC 25 |
61173741 ps |
| T1013 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.9985598 |
|
|
Feb 09 08:32:47 AM UTC 25 |
Feb 09 08:32:50 AM UTC 25 |
33286631 ps |
| T116 |
/workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.3187569550 |
|
|
Feb 09 08:32:48 AM UTC 25 |
Feb 09 08:32:51 AM UTC 25 |
96970638 ps |