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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1119
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T1014 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1701974003 Feb 09 08:32:47 AM UTC 25 Feb 09 08:32:51 AM UTC 25 117163528 ps
T1015 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.2585560144 Feb 09 08:32:49 AM UTC 25 Feb 09 08:32:51 AM UTC 25 22304012 ps
T1016 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1259411315 Feb 09 08:32:49 AM UTC 25 Feb 09 08:32:51 AM UTC 25 49756345 ps
T128 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.664386109 Feb 09 08:32:48 AM UTC 25 Feb 09 08:32:51 AM UTC 25 36732374 ps
T68 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2338894985 Feb 09 08:32:47 AM UTC 25 Feb 09 08:32:51 AM UTC 25 338539227 ps
T1017 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3118733124 Feb 09 08:32:46 AM UTC 25 Feb 09 08:32:51 AM UTC 25 139742550 ps
T69 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2167916975 Feb 09 08:32:49 AM UTC 25 Feb 09 08:32:52 AM UTC 25 199179152 ps
T117 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.3300837960 Feb 09 08:32:50 AM UTC 25 Feb 09 08:32:52 AM UTC 25 55093383 ps
T1018 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3730505826 Feb 09 08:32:50 AM UTC 25 Feb 09 08:32:52 AM UTC 25 39307858 ps
T1019 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1798972558 Feb 09 08:32:50 AM UTC 25 Feb 09 08:32:52 AM UTC 25 92965107 ps
T1020 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3246746002 Feb 09 08:32:50 AM UTC 25 Feb 09 08:32:53 AM UTC 25 224933645 ps
T1021 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.2955779142 Feb 09 08:32:49 AM UTC 25 Feb 09 08:32:53 AM UTC 25 50869874 ps
T1022 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.1355143877 Feb 09 08:32:50 AM UTC 25 Feb 09 08:32:53 AM UTC 25 79401406 ps
T181 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.4093471763 Feb 09 08:32:51 AM UTC 25 Feb 09 08:32:53 AM UTC 25 83411664 ps
T1023 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.3053680023 Feb 09 08:32:51 AM UTC 25 Feb 09 08:32:53 AM UTC 25 22677355 ps
T1024 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.4024535115 Feb 09 08:32:51 AM UTC 25 Feb 09 08:32:53 AM UTC 25 77092621 ps
T1025 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2316000504 Feb 09 08:32:52 AM UTC 25 Feb 09 08:32:54 AM UTC 25 44352545 ps
T1026 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1824086164 Feb 09 08:32:51 AM UTC 25 Feb 09 08:32:54 AM UTC 25 131649176 ps
T1027 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3570575938 Feb 09 08:32:52 AM UTC 25 Feb 09 08:32:54 AM UTC 25 73785890 ps
T118 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2961650622 Feb 09 08:32:52 AM UTC 25 Feb 09 08:32:54 AM UTC 25 43098503 ps
T1028 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4134948188 Feb 09 08:32:52 AM UTC 25 Feb 09 08:32:55 AM UTC 25 28769309 ps
T1029 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.4159999970 Feb 09 08:32:51 AM UTC 25 Feb 09 08:32:55 AM UTC 25 72440567 ps
T175 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.80810006 Feb 09 08:32:52 AM UTC 25 Feb 09 08:32:55 AM UTC 25 196513204 ps
T1030 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.2033284342 Feb 09 08:32:53 AM UTC 25 Feb 09 08:32:56 AM UTC 25 33085585 ps
T1031 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.2107433739 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:56 AM UTC 25 25892376 ps
T1032 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.4154341126 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:56 AM UTC 25 21005583 ps
T1033 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.986850354 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:56 AM UTC 25 18040831 ps
T1034 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.4039925471 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:56 AM UTC 25 73523307 ps
T1035 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3923083217 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:56 AM UTC 25 88847720 ps
T1036 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.4258966267 Feb 09 08:32:52 AM UTC 25 Feb 09 08:32:56 AM UTC 25 167919649 ps
T1037 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1876097787 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:56 AM UTC 25 102843864 ps
T176 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.782028111 Feb 09 08:32:53 AM UTC 25 Feb 09 08:32:57 AM UTC 25 176612834 ps
T1038 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.789645017 Feb 09 08:32:55 AM UTC 25 Feb 09 08:32:57 AM UTC 25 28269947 ps
T1039 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1956276198 Feb 09 08:32:55 AM UTC 25 Feb 09 08:32:57 AM UTC 25 40722457 ps
T1040 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3093420949 Feb 09 08:32:54 AM UTC 25 Feb 09 08:32:58 AM UTC 25 45387808 ps
T1041 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2168010184 Feb 09 08:33:11 AM UTC 25 Feb 09 08:33:13 AM UTC 25 82178358 ps
T1042 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1743666630 Feb 09 08:32:55 AM UTC 25 Feb 09 08:32:58 AM UTC 25 241418958 ps
T1043 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1459903553 Feb 09 08:32:56 AM UTC 25 Feb 09 08:32:58 AM UTC 25 20219639 ps
T1044 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.795429349 Feb 09 08:32:56 AM UTC 25 Feb 09 08:32:58 AM UTC 25 17757017 ps
T1045 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1045695215 Feb 09 08:32:56 AM UTC 25 Feb 09 08:32:58 AM UTC 25 42368176 ps
T1046 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3156295604 Feb 09 08:32:55 AM UTC 25 Feb 09 08:32:59 AM UTC 25 119762603 ps
T1047 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3163036203 Feb 09 08:32:56 AM UTC 25 Feb 09 08:32:59 AM UTC 25 104218536 ps
T1048 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2378417036 Feb 09 08:32:57 AM UTC 25 Feb 09 08:32:59 AM UTC 25 43346715 ps
T119 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.1323128780 Feb 09 08:32:57 AM UTC 25 Feb 09 08:32:59 AM UTC 25 27186095 ps
T1049 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3289568640 Feb 09 08:32:57 AM UTC 25 Feb 09 08:33:00 AM UTC 25 30035259 ps
T1050 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2099949622 Feb 09 08:32:57 AM UTC 25 Feb 09 08:33:00 AM UTC 25 69981801 ps
T1051 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3702183937 Feb 09 08:32:57 AM UTC 25 Feb 09 08:33:00 AM UTC 25 249888112 ps
T1052 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1658107323 Feb 09 08:32:57 AM UTC 25 Feb 09 08:33:00 AM UTC 25 111742976 ps
T1053 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.1638887138 Feb 09 08:32:56 AM UTC 25 Feb 09 08:33:01 AM UTC 25 105136499 ps
T1054 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1383691218 Feb 09 08:32:59 AM UTC 25 Feb 09 08:33:01 AM UTC 25 23859958 ps
T1055 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2772029897 Feb 09 08:32:59 AM UTC 25 Feb 09 08:33:01 AM UTC 25 64918145 ps
T1056 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.650673108 Feb 09 08:32:59 AM UTC 25 Feb 09 08:33:01 AM UTC 25 48006569 ps
T1057 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1043638173 Feb 09 08:32:59 AM UTC 25 Feb 09 08:33:01 AM UTC 25 28082744 ps
T1058 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1053423344 Feb 09 08:32:57 AM UTC 25 Feb 09 08:33:01 AM UTC 25 81294256 ps
T70 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.412202331 Feb 09 08:32:59 AM UTC 25 Feb 09 08:33:01 AM UTC 25 225357595 ps
T1059 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1052940607 Feb 09 08:33:00 AM UTC 25 Feb 09 08:33:02 AM UTC 25 56758189 ps
T1060 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2658870682 Feb 09 08:33:00 AM UTC 25 Feb 09 08:33:02 AM UTC 25 47959387 ps
T1061 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2299354270 Feb 09 08:33:00 AM UTC 25 Feb 09 08:33:03 AM UTC 25 49409233 ps
T1062 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.2772612882 Feb 09 08:32:59 AM UTC 25 Feb 09 08:33:03 AM UTC 25 54193674 ps
T1063 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.611195012 Feb 09 08:33:00 AM UTC 25 Feb 09 08:33:03 AM UTC 25 173122505 ps
T1064 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.580378321 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:03 AM UTC 25 86789703 ps
T1065 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3872240100 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:03 AM UTC 25 43115096 ps
T1066 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.241360081 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:03 AM UTC 25 64328951 ps
T1067 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.2405121555 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:03 AM UTC 25 34192829 ps
T1068 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.591438712 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:03 AM UTC 25 28986939 ps
T1069 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2552615161 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:04 AM UTC 25 489016773 ps
T1070 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3954287785 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:04 AM UTC 25 148879529 ps
T1071 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1975252177 Feb 09 08:33:00 AM UTC 25 Feb 09 08:33:04 AM UTC 25 175712951 ps
T1072 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2166462532 Feb 09 08:33:01 AM UTC 25 Feb 09 08:33:05 AM UTC 25 461418688 ps
T1073 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3942278158 Feb 09 08:33:02 AM UTC 25 Feb 09 08:33:05 AM UTC 25 23096901 ps
T1074 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.474564350 Feb 09 08:33:02 AM UTC 25 Feb 09 08:33:05 AM UTC 25 33807802 ps
T1075 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3708831797 Feb 09 08:33:03 AM UTC 25 Feb 09 08:33:05 AM UTC 25 35597370 ps
T1076 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.4186761872 Feb 09 08:33:03 AM UTC 25 Feb 09 08:33:06 AM UTC 25 74390766 ps
T1077 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3412240725 Feb 09 08:33:04 AM UTC 25 Feb 09 08:33:06 AM UTC 25 41198698 ps
T1078 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.1757997122 Feb 09 08:33:04 AM UTC 25 Feb 09 08:33:06 AM UTC 25 55075008 ps
T1079 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.97186805 Feb 09 08:33:04 AM UTC 25 Feb 09 08:33:06 AM UTC 25 50478053 ps
T177 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.192183375 Feb 09 08:33:03 AM UTC 25 Feb 09 08:33:06 AM UTC 25 207720099 ps
T1080 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.817281469 Feb 09 08:33:04 AM UTC 25 Feb 09 08:33:06 AM UTC 25 37430333 ps
T1081 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.633688972 Feb 09 08:33:04 AM UTC 25 Feb 09 08:33:06 AM UTC 25 129289793 ps
T1082 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2398449690 Feb 09 08:33:05 AM UTC 25 Feb 09 08:33:07 AM UTC 25 52250802 ps
T120 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3008528571 Feb 09 08:33:05 AM UTC 25 Feb 09 08:33:07 AM UTC 25 55331843 ps
T1083 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3184355648 Feb 09 08:33:05 AM UTC 25 Feb 09 08:33:07 AM UTC 25 65611749 ps
T1084 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1927192387 Feb 09 08:33:05 AM UTC 25 Feb 09 08:33:07 AM UTC 25 15741843 ps
T1085 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.564578544 Feb 09 08:33:04 AM UTC 25 Feb 09 08:33:08 AM UTC 25 85358910 ps
T1086 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3321309210 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:08 AM UTC 25 25757696 ps
T1087 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1641909671 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:08 AM UTC 25 18649379 ps
T1088 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1231035363 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:08 AM UTC 25 49924720 ps
T122 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.158125257 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:08 AM UTC 25 24625052 ps
T1089 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2011277704 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:09 AM UTC 25 77506469 ps
T1090 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1910544750 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:09 AM UTC 25 112842757 ps
T1091 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4217932472 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:09 AM UTC 25 226893089 ps
T1092 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3151283994 Feb 09 08:33:06 AM UTC 25 Feb 09 08:33:09 AM UTC 25 48007669 ps
T1093 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.411764692 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:13 AM UTC 25 22589570 ps
T1094 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1675590272 Feb 09 08:33:08 AM UTC 25 Feb 09 08:33:10 AM UTC 25 19145176 ps
T1095 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4197672907 Feb 09 08:33:08 AM UTC 25 Feb 09 08:33:10 AM UTC 25 28190082 ps
T1096 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2314307908 Feb 09 08:33:08 AM UTC 25 Feb 09 08:33:10 AM UTC 25 21755267 ps
T1097 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.243302915 Feb 09 08:33:08 AM UTC 25 Feb 09 08:33:10 AM UTC 25 36564426 ps
T1098 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2344241931 Feb 09 08:33:08 AM UTC 25 Feb 09 08:33:10 AM UTC 25 89983579 ps
T1099 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2818516858 Feb 09 08:33:05 AM UTC 25 Feb 09 08:33:10 AM UTC 25 139629828 ps
T1100 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.548020927 Feb 09 08:33:09 AM UTC 25 Feb 09 08:33:11 AM UTC 25 46058792 ps
T1101 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.1120358723 Feb 09 08:33:09 AM UTC 25 Feb 09 08:33:11 AM UTC 25 45364549 ps
T1102 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3495466528 Feb 09 08:33:09 AM UTC 25 Feb 09 08:33:11 AM UTC 25 28596781 ps
T1103 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2208039654 Feb 09 08:33:09 AM UTC 25 Feb 09 08:33:11 AM UTC 25 15996274 ps
T1104 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3241756550 Feb 09 08:33:09 AM UTC 25 Feb 09 08:33:11 AM UTC 25 84043287 ps
T1105 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.66989386 Feb 09 08:33:09 AM UTC 25 Feb 09 08:33:11 AM UTC 25 26760806 ps
T1106 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.891402559 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:12 AM UTC 25 30781231 ps
T1107 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3076189370 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:12 AM UTC 25 23102222 ps
T1108 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.848098780 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:12 AM UTC 25 51522255 ps
T1109 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.1094699863 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:12 AM UTC 25 51803710 ps
T1110 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3438179719 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:13 AM UTC 25 20152406 ps
T1111 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1586171289 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:13 AM UTC 25 19793487 ps
T1112 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.1830735140 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:13 AM UTC 25 45595762 ps
T1113 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.1021271149 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:13 AM UTC 25 19574695 ps
T1114 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2390854245 Feb 09 08:33:10 AM UTC 25 Feb 09 08:33:13 AM UTC 25 19463012 ps
T1115 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.3611155367 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:14 AM UTC 25 55642910 ps
T1116 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.3995136185 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:14 AM UTC 25 17522979 ps
T1117 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2227138310 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:14 AM UTC 25 18189952 ps
T1118 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.529940504 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:14 AM UTC 25 71817908 ps
T1119 /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.1277457594 Feb 09 08:33:12 AM UTC 25 Feb 09 08:33:14 AM UTC 25 19228494 ps

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2979780305
Short name T5
Test name
Test status
Simulation time 311769473 ps
CPU time 1.51 seconds
Started Feb 09 02:03:36 PM UTC 25
Finished Feb 09 02:03:38 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979780305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2979780305
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1611411768
Short name T29
Test name
Test status
Simulation time 101029283 ps
CPU time 1.73 seconds
Started Feb 09 02:03:39 PM UTC 25
Finished Feb 09 02:03:42 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611411768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1611411768
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.1172453987
Short name T15
Test name
Test status
Simulation time 530270203 ps
CPU time 1.52 seconds
Started Feb 09 02:03:40 PM UTC 25
Finished Feb 09 02:03:43 PM UTC 25
Peak memory 211276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172453987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.1172453987
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.175581972
Short name T22
Test name
Test status
Simulation time 457248952 ps
CPU time 1.8 seconds
Started Feb 09 02:03:44 PM UTC 25
Finished Feb 09 02:03:47 PM UTC 25
Peak memory 236992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175581972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.175581972
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815018880
Short name T79
Test name
Test status
Simulation time 787760899 ps
CPU time 3.09 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:46 PM UTC 25
Peak memory 211516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815018880 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815018880
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.643249170
Short name T49
Test name
Test status
Simulation time 10996289647 ps
CPU time 31.9 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 211628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=643249170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_r
eset.643249170
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.504057679
Short name T57
Test name
Test status
Simulation time 156312629 ps
CPU time 1.78 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:41 AM UTC 25
Peak memory 211608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504057679 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.504057679
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.623191150
Short name T40
Test name
Test status
Simulation time 45711843 ps
CPU time 0.92 seconds
Started Feb 09 02:03:40 PM UTC 25
Finished Feb 09 02:03:42 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623191150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.623191150
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.2885248141
Short name T52
Test name
Test status
Simulation time 41025330 ps
CPU time 0.92 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:40 AM UTC 25
Peak memory 208592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885248141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2885248141
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3576241416
Short name T61
Test name
Test status
Simulation time 168385216 ps
CPU time 1.43 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576241416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.3576241416
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.4104001944
Short name T11
Test name
Test status
Simulation time 1266022400 ps
CPU time 1.17 seconds
Started Feb 09 02:03:38 PM UTC 25
Finished Feb 09 02:03:41 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104001944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.4104001944
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.535163161
Short name T114
Test name
Test status
Simulation time 44982035 ps
CPU time 0.94 seconds
Started Feb 09 08:32:44 AM UTC 25
Finished Feb 09 08:32:46 AM UTC 25
Peak memory 207824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535163161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.535163161
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.3118733124
Short name T1017
Test name
Test status
Simulation time 139742550 ps
CPU time 3.95 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 211932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118733124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3118733124
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.872982666
Short name T133
Test name
Test status
Simulation time 123478203 ps
CPU time 0.93 seconds
Started Feb 09 02:03:57 PM UTC 25
Finished Feb 09 02:03:59 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872982666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.872982666
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.452882707
Short name T42
Test name
Test status
Simulation time 159670063 ps
CPU time 1.19 seconds
Started Feb 09 02:03:51 PM UTC 25
Finished Feb 09 02:03:53 PM UTC 25
Peak memory 208508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452882707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.452882707
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.316024620
Short name T76
Test name
Test status
Simulation time 195774026 ps
CPU time 2.71 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:47 AM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316024620 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.316024620
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.462882686
Short name T54
Test name
Test status
Simulation time 20499680 ps
CPU time 0.91 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:40 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462882686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.462882686
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.782028111
Short name T176
Test name
Test status
Simulation time 176612834 ps
CPU time 2.16 seconds
Started Feb 09 08:32:53 AM UTC 25
Finished Feb 09 08:32:57 AM UTC 25
Peak memory 211884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782028111 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.782028111
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.3963635269
Short name T129
Test name
Test status
Simulation time 1190525883 ps
CPU time 3.4 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:03:54 PM UTC 25
Peak memory 211216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963635269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.3963635269
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.4102155260
Short name T186
Test name
Test status
Simulation time 63691484 ps
CPU time 0.73 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102155260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.4102155260
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2036951578
Short name T191
Test name
Test status
Simulation time 90322319 ps
CPU time 0.85 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 210720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036951578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.2036951578
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.320155180
Short name T51
Test name
Test status
Simulation time 146395694 ps
CPU time 2.44 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:42 AM UTC 25
Peak memory 211680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320155180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.320155180
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.412202331
Short name T70
Test name
Test status
Simulation time 225357595 ps
CPU time 1.34 seconds
Started Feb 09 08:32:59 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 210208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412202331 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.412202331
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2157180450
Short name T17
Test name
Test status
Simulation time 39981765 ps
CPU time 1.04 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:45 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157180450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.2157180450
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3513931804
Short name T63
Test name
Test status
Simulation time 464179365 ps
CPU time 1.59 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:41 AM UTC 25
Peak memory 210508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513931804 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.3513931804
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3346109123
Short name T183
Test name
Test status
Simulation time 131919112 ps
CPU time 2.38 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:41 AM UTC 25
Peak memory 211808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346109123 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3346109123
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3632372615
Short name T53
Test name
Test status
Simulation time 27660449 ps
CPU time 1 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:40 AM UTC 25
Peak memory 207664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632372615 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3632372615
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1738363186
Short name T48
Test name
Test status
Simulation time 84759431 ps
CPU time 1.78 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:41 AM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738363
186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1738363186
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.3327182573
Short name T55
Test name
Test status
Simulation time 29174038 ps
CPU time 0.92 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:40 AM UTC 25
Peak memory 209592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327182573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.3327182573
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2727780035
Short name T62
Test name
Test status
Simulation time 115056774 ps
CPU time 1.31 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:40 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727780035 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.2727780035
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.592512922
Short name T66
Test name
Test status
Simulation time 192640532 ps
CPU time 3.02 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:42 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592512922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.592512922
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4021461716
Short name T47
Test name
Test status
Simulation time 185067611 ps
CPU time 1.87 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:41 AM UTC 25
Peak memory 211748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021461716 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.4021461716
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1782613000
Short name T182
Test name
Test status
Simulation time 78423049 ps
CPU time 1.02 seconds
Started Feb 09 08:32:40 AM UTC 25
Finished Feb 09 08:32:42 AM UTC 25
Peak memory 209716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782613000 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1782613000
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.868068250
Short name T184
Test name
Test status
Simulation time 268242606 ps
CPU time 3.26 seconds
Started Feb 09 08:32:40 AM UTC 25
Finished Feb 09 08:32:45 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868068250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.868068250
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1071944306
Short name T56
Test name
Test status
Simulation time 27174828 ps
CPU time 0.99 seconds
Started Feb 09 08:32:38 AM UTC 25
Finished Feb 09 08:32:40 AM UTC 25
Peak memory 208788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071944306 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.1071944306
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.529244003
Short name T77
Test name
Test status
Simulation time 53876965 ps
CPU time 1.39 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:45 AM UTC 25
Peak memory 210272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5292440
03 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.529244003
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1911303951
Short name T113
Test name
Test status
Simulation time 57014713 ps
CPU time 1.01 seconds
Started Feb 09 08:32:40 AM UTC 25
Finished Feb 09 08:32:42 AM UTC 25
Peak memory 208884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911303951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1911303951
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2218256181
Short name T124
Test name
Test status
Simulation time 36714578 ps
CPU time 1.26 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:44 AM UTC 25
Peak memory 210512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218256181 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.2218256181
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1956276198
Short name T1039
Test name
Test status
Simulation time 40722457 ps
CPU time 1.2 seconds
Started Feb 09 08:32:55 AM UTC 25
Finished Feb 09 08:32:57 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956276
198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.1956276198
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.986850354
Short name T1033
Test name
Test status
Simulation time 18040831 ps
CPU time 0.88 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 209248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986850354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.986850354
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.4154341126
Short name T1032
Test name
Test status
Simulation time 21005583 ps
CPU time 0.95 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154341126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.4154341126
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.789645017
Short name T1038
Test name
Test status
Simulation time 28269947 ps
CPU time 1.06 seconds
Started Feb 09 08:32:55 AM UTC 25
Finished Feb 09 08:32:57 AM UTC 25
Peak memory 209480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789645017 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.789645017
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.3093420949
Short name T1040
Test name
Test status
Simulation time 45387808 ps
CPU time 2.7 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:58 AM UTC 25
Peak memory 211636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093420949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3093420949
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1876097787
Short name T1037
Test name
Test status
Simulation time 102843864 ps
CPU time 1.49 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 211760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876097787 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.1876097787
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.3163036203
Short name T1047
Test name
Test status
Simulation time 104218536 ps
CPU time 1.69 seconds
Started Feb 09 08:32:56 AM UTC 25
Finished Feb 09 08:32:59 AM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163036
203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.3163036203
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1459903553
Short name T1043
Test name
Test status
Simulation time 20219639 ps
CPU time 0.8 seconds
Started Feb 09 08:32:56 AM UTC 25
Finished Feb 09 08:32:58 AM UTC 25
Peak memory 208744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459903553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.1459903553
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.795429349
Short name T1044
Test name
Test status
Simulation time 17757017 ps
CPU time 0.94 seconds
Started Feb 09 08:32:56 AM UTC 25
Finished Feb 09 08:32:58 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795429349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.795429349
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1045695215
Short name T1045
Test name
Test status
Simulation time 42368176 ps
CPU time 1.05 seconds
Started Feb 09 08:32:56 AM UTC 25
Finished Feb 09 08:32:58 AM UTC 25
Peak memory 210568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045695215 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.1045695215
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3156295604
Short name T1046
Test name
Test status
Simulation time 119762603 ps
CPU time 2.44 seconds
Started Feb 09 08:32:55 AM UTC 25
Finished Feb 09 08:32:59 AM UTC 25
Peak memory 211896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156295604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3156295604
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1743666630
Short name T1042
Test name
Test status
Simulation time 241418958 ps
CPU time 1.69 seconds
Started Feb 09 08:32:55 AM UTC 25
Finished Feb 09 08:32:58 AM UTC 25
Peak memory 210204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743666630 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.1743666630
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2099949622
Short name T1050
Test name
Test status
Simulation time 69981801 ps
CPU time 1.11 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:33:00 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099949
622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.2099949622
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.1323128780
Short name T119
Test name
Test status
Simulation time 27186095 ps
CPU time 0.83 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:32:59 AM UTC 25
Peak memory 208768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323128780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1323128780
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2378417036
Short name T1048
Test name
Test status
Simulation time 43346715 ps
CPU time 0.81 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:32:59 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378417036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2378417036
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3289568640
Short name T1049
Test name
Test status
Simulation time 30035259 ps
CPU time 1 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:33:00 AM UTC 25
Peak memory 210268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289568640 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.3289568640
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.1638887138
Short name T1053
Test name
Test status
Simulation time 105136499 ps
CPU time 3.15 seconds
Started Feb 09 08:32:56 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638887138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.1638887138
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3702183937
Short name T1051
Test name
Test status
Simulation time 249888112 ps
CPU time 1.67 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:33:00 AM UTC 25
Peak memory 211732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702183937 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.3702183937
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.650673108
Short name T1056
Test name
Test status
Simulation time 48006569 ps
CPU time 0.88 seconds
Started Feb 09 08:32:59 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 211736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6506731
08 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.650673108
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2772029897
Short name T1055
Test name
Test status
Simulation time 64918145 ps
CPU time 0.91 seconds
Started Feb 09 08:32:59 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772029897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2772029897
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1383691218
Short name T1054
Test name
Test status
Simulation time 23859958 ps
CPU time 0.85 seconds
Started Feb 09 08:32:59 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383691218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1383691218
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.1043638173
Short name T1057
Test name
Test status
Simulation time 28082744 ps
CPU time 1.12 seconds
Started Feb 09 08:32:59 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 210204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043638173 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.1043638173
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1053423344
Short name T1058
Test name
Test status
Simulation time 81294256 ps
CPU time 2.24 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:33:01 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053423344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1053423344
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1658107323
Short name T1052
Test name
Test status
Simulation time 111742976 ps
CPU time 1.67 seconds
Started Feb 09 08:32:57 AM UTC 25
Finished Feb 09 08:33:00 AM UTC 25
Peak memory 211788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658107323 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.1658107323
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.611195012
Short name T1063
Test name
Test status
Simulation time 173122505 ps
CPU time 1.84 seconds
Started Feb 09 08:33:00 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 211680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6111950
12 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.611195012
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1052940607
Short name T1059
Test name
Test status
Simulation time 56758189 ps
CPU time 0.75 seconds
Started Feb 09 08:33:00 AM UTC 25
Finished Feb 09 08:33:02 AM UTC 25
Peak memory 207620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052940607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1052940607
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.2658870682
Short name T1060
Test name
Test status
Simulation time 47959387 ps
CPU time 0.87 seconds
Started Feb 09 08:33:00 AM UTC 25
Finished Feb 09 08:33:02 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658870682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.2658870682
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2299354270
Short name T1061
Test name
Test status
Simulation time 49409233 ps
CPU time 1.47 seconds
Started Feb 09 08:33:00 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 210508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299354270 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.2299354270
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.2772612882
Short name T1062
Test name
Test status
Simulation time 54193674 ps
CPU time 2.72 seconds
Started Feb 09 08:32:59 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 211672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772612882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.2772612882
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.241360081
Short name T1066
Test name
Test status
Simulation time 64328951 ps
CPU time 0.93 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413600
81 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.241360081
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3872240100
Short name T1065
Test name
Test status
Simulation time 43115096 ps
CPU time 0.95 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 208564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872240100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3872240100
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.580378321
Short name T1064
Test name
Test status
Simulation time 86789703 ps
CPU time 0.83 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580378321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.580378321
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.591438712
Short name T1068
Test name
Test status
Simulation time 28986939 ps
CPU time 1.07 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 208892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591438712 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.591438712
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.1975252177
Short name T1071
Test name
Test status
Simulation time 175712951 ps
CPU time 2.68 seconds
Started Feb 09 08:33:00 AM UTC 25
Finished Feb 09 08:33:04 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975252177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1975252177
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2552615161
Short name T1069
Test name
Test status
Simulation time 489016773 ps
CPU time 1.55 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:04 AM UTC 25
Peak memory 211732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552615161 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.2552615161
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3708831797
Short name T1075
Test name
Test status
Simulation time 35597370 ps
CPU time 1.19 seconds
Started Feb 09 08:33:03 AM UTC 25
Finished Feb 09 08:33:05 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708831
797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3708831797
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.3942278158
Short name T1073
Test name
Test status
Simulation time 23096901 ps
CPU time 0.97 seconds
Started Feb 09 08:33:02 AM UTC 25
Finished Feb 09 08:33:05 AM UTC 25
Peak memory 207700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942278158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3942278158
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.2405121555
Short name T1067
Test name
Test status
Simulation time 34192829 ps
CPU time 0.86 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:03 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405121555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.2405121555
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.474564350
Short name T1074
Test name
Test status
Simulation time 33807802 ps
CPU time 1.14 seconds
Started Feb 09 08:33:02 AM UTC 25
Finished Feb 09 08:33:05 AM UTC 25
Peak memory 209744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474564350 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.474564350
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.2166462532
Short name T1072
Test name
Test status
Simulation time 461418688 ps
CPU time 2.21 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:05 AM UTC 25
Peak memory 211636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166462532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.2166462532
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3954287785
Short name T1070
Test name
Test status
Simulation time 148879529 ps
CPU time 1.22 seconds
Started Feb 09 08:33:01 AM UTC 25
Finished Feb 09 08:33:04 AM UTC 25
Peak memory 210204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954287785 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.3954287785
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.817281469
Short name T1080
Test name
Test status
Simulation time 37430333 ps
CPU time 1.07 seconds
Started Feb 09 08:33:04 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8172814
69 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.817281469
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.97186805
Short name T1079
Test name
Test status
Simulation time 50478053 ps
CPU time 0.95 seconds
Started Feb 09 08:33:04 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 209464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97186805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.97186805
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.1757997122
Short name T1078
Test name
Test status
Simulation time 55075008 ps
CPU time 0.94 seconds
Started Feb 09 08:33:04 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757997122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1757997122
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3412240725
Short name T1077
Test name
Test status
Simulation time 41198698 ps
CPU time 0.75 seconds
Started Feb 09 08:33:04 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 210208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412240725 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.3412240725
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.4186761872
Short name T1076
Test name
Test status
Simulation time 74390766 ps
CPU time 2 seconds
Started Feb 09 08:33:03 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 211744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186761872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.4186761872
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.192183375
Short name T177
Test name
Test status
Simulation time 207720099 ps
CPU time 2.01 seconds
Started Feb 09 08:33:03 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 210208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192183375 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.192183375
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3184355648
Short name T1083
Test name
Test status
Simulation time 65611749 ps
CPU time 1.1 seconds
Started Feb 09 08:33:05 AM UTC 25
Finished Feb 09 08:33:07 AM UTC 25
Peak memory 210272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184355
648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3184355648
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.3008528571
Short name T120
Test name
Test status
Simulation time 55331843 ps
CPU time 0.93 seconds
Started Feb 09 08:33:05 AM UTC 25
Finished Feb 09 08:33:07 AM UTC 25
Peak memory 207700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008528571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3008528571
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1927192387
Short name T1084
Test name
Test status
Simulation time 15741843 ps
CPU time 0.94 seconds
Started Feb 09 08:33:05 AM UTC 25
Finished Feb 09 08:33:07 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927192387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1927192387
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2398449690
Short name T1082
Test name
Test status
Simulation time 52250802 ps
CPU time 0.84 seconds
Started Feb 09 08:33:05 AM UTC 25
Finished Feb 09 08:33:07 AM UTC 25
Peak memory 210328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398449690 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.2398449690
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.564578544
Short name T1085
Test name
Test status
Simulation time 85358910 ps
CPU time 3.17 seconds
Started Feb 09 08:33:04 AM UTC 25
Finished Feb 09 08:33:08 AM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564578544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.564578544
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.633688972
Short name T1081
Test name
Test status
Simulation time 129289793 ps
CPU time 1.31 seconds
Started Feb 09 08:33:04 AM UTC 25
Finished Feb 09 08:33:06 AM UTC 25
Peak memory 210208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633688972 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.633688972
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3151283994
Short name T1092
Test name
Test status
Simulation time 48007669 ps
CPU time 1.4 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:09 AM UTC 25
Peak memory 211688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151283
994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3151283994
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.158125257
Short name T122
Test name
Test status
Simulation time 24625052 ps
CPU time 1.01 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:08 AM UTC 25
Peak memory 210640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158125257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.158125257
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3321309210
Short name T1086
Test name
Test status
Simulation time 25757696 ps
CPU time 0.94 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:08 AM UTC 25
Peak memory 207744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321309210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3321309210
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1910544750
Short name T1090
Test name
Test status
Simulation time 112842757 ps
CPU time 1.11 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:09 AM UTC 25
Peak memory 209476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910544750 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.1910544750
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.2818516858
Short name T1099
Test name
Test status
Simulation time 139629828 ps
CPU time 3.69 seconds
Started Feb 09 08:33:05 AM UTC 25
Finished Feb 09 08:33:10 AM UTC 25
Peak memory 211604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818516858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2818516858
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4217932472
Short name T1091
Test name
Test status
Simulation time 226893089 ps
CPU time 1.46 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:09 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217932472 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.4217932472
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.695185686
Short name T1004
Test name
Test status
Simulation time 151481756 ps
CPU time 1.52 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:45 AM UTC 25
Peak memory 210308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695185686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.695185686
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3793869915
Short name T1006
Test name
Test status
Simulation time 167344325 ps
CPU time 2.65 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:46 AM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793869915 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3793869915
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1405764395
Short name T146
Test name
Test status
Simulation time 60779100 ps
CPU time 0.89 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:44 AM UTC 25
Peak memory 207700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405764395 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1405764395
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1922180718
Short name T73
Test name
Test status
Simulation time 75466349 ps
CPU time 1.43 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:45 AM UTC 25
Peak memory 211736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922180
718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1922180718
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.3975537135
Short name T123
Test name
Test status
Simulation time 16827428 ps
CPU time 0.99 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:44 AM UTC 25
Peak memory 208560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975537135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3975537135
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.2909671775
Short name T178
Test name
Test status
Simulation time 23669965 ps
CPU time 0.95 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:44 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909671775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.2909671775
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1842251601
Short name T125
Test name
Test status
Simulation time 45252357 ps
CPU time 1.05 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:45 AM UTC 25
Peak memory 209996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842251601 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.1842251601
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.1735943805
Short name T67
Test name
Test status
Simulation time 223050136 ps
CPU time 3.48 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:47 AM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735943805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1735943805
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.543799887
Short name T58
Test name
Test status
Simulation time 499695377 ps
CPU time 2.45 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:46 AM UTC 25
Peak memory 211628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543799887 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.543799887
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1231035363
Short name T1088
Test name
Test status
Simulation time 49924720 ps
CPU time 0.83 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:08 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231035363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1231035363
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2011277704
Short name T1089
Test name
Test status
Simulation time 77506469 ps
CPU time 0.89 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:09 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011277704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2011277704
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.1641909671
Short name T1087
Test name
Test status
Simulation time 18649379 ps
CPU time 0.81 seconds
Started Feb 09 08:33:06 AM UTC 25
Finished Feb 09 08:33:08 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641909671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1641909671
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.4197672907
Short name T1095
Test name
Test status
Simulation time 28190082 ps
CPU time 0.81 seconds
Started Feb 09 08:33:08 AM UTC 25
Finished Feb 09 08:33:10 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197672907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.4197672907
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.1675590272
Short name T1094
Test name
Test status
Simulation time 19145176 ps
CPU time 0.81 seconds
Started Feb 09 08:33:08 AM UTC 25
Finished Feb 09 08:33:10 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675590272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.1675590272
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2314307908
Short name T1096
Test name
Test status
Simulation time 21755267 ps
CPU time 0.86 seconds
Started Feb 09 08:33:08 AM UTC 25
Finished Feb 09 08:33:10 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314307908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.2314307908
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.243302915
Short name T1097
Test name
Test status
Simulation time 36564426 ps
CPU time 0.88 seconds
Started Feb 09 08:33:08 AM UTC 25
Finished Feb 09 08:33:10 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243302915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.243302915
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2344241931
Short name T1098
Test name
Test status
Simulation time 89983579 ps
CPU time 0.92 seconds
Started Feb 09 08:33:08 AM UTC 25
Finished Feb 09 08:33:10 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344241931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2344241931
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.1120358723
Short name T1101
Test name
Test status
Simulation time 45364549 ps
CPU time 0.8 seconds
Started Feb 09 08:33:09 AM UTC 25
Finished Feb 09 08:33:11 AM UTC 25
Peak memory 207592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120358723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.1120358723
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.2208039654
Short name T1103
Test name
Test status
Simulation time 15996274 ps
CPU time 0.88 seconds
Started Feb 09 08:33:09 AM UTC 25
Finished Feb 09 08:33:11 AM UTC 25
Peak memory 207580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208039654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.2208039654
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1423936259
Short name T1007
Test name
Test status
Simulation time 83164198 ps
CPU time 0.97 seconds
Started Feb 09 08:32:45 AM UTC 25
Finished Feb 09 08:32:47 AM UTC 25
Peak memory 209932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423936259 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1423936259
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.4216984996
Short name T121
Test name
Test status
Simulation time 43464023 ps
CPU time 2.04 seconds
Started Feb 09 08:32:45 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 211924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216984996 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.4216984996
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.943113994
Short name T1005
Test name
Test status
Simulation time 43637969 ps
CPU time 0.94 seconds
Started Feb 09 08:32:44 AM UTC 25
Finished Feb 09 08:32:46 AM UTC 25
Peak memory 207408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943113994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.943113994
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4050411281
Short name T1009
Test name
Test status
Simulation time 52171353 ps
CPU time 1.25 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 211736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050411
281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.4050411281
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.1918591669
Short name T180
Test name
Test status
Simulation time 46286940 ps
CPU time 0.92 seconds
Started Feb 09 08:32:44 AM UTC 25
Finished Feb 09 08:32:46 AM UTC 25
Peak memory 207456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918591669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1918591669
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2022801213
Short name T126
Test name
Test status
Simulation time 29886650 ps
CPU time 0.96 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 210512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022801213 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.2022801213
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3656020522
Short name T71
Test name
Test status
Simulation time 425418753 ps
CPU time 1.96 seconds
Started Feb 09 08:32:42 AM UTC 25
Finished Feb 09 08:32:46 AM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656020522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3656020522
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.3495466528
Short name T1102
Test name
Test status
Simulation time 28596781 ps
CPU time 0.86 seconds
Started Feb 09 08:33:09 AM UTC 25
Finished Feb 09 08:33:11 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495466528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3495466528
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.66989386
Short name T1105
Test name
Test status
Simulation time 26760806 ps
CPU time 0.94 seconds
Started Feb 09 08:33:09 AM UTC 25
Finished Feb 09 08:33:11 AM UTC 25
Peak memory 207644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66989386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM
_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.66989386
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.548020927
Short name T1100
Test name
Test status
Simulation time 46058792 ps
CPU time 0.73 seconds
Started Feb 09 08:33:09 AM UTC 25
Finished Feb 09 08:33:11 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548020927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.548020927
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.3241756550
Short name T1104
Test name
Test status
Simulation time 84043287 ps
CPU time 0.83 seconds
Started Feb 09 08:33:09 AM UTC 25
Finished Feb 09 08:33:11 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241756550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3241756550
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.848098780
Short name T1108
Test name
Test status
Simulation time 51522255 ps
CPU time 0.93 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:12 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848098780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.848098780
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.1094699863
Short name T1109
Test name
Test status
Simulation time 51803710 ps
CPU time 0.95 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:12 AM UTC 25
Peak memory 207728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094699863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1094699863
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3076189370
Short name T1107
Test name
Test status
Simulation time 23102222 ps
CPU time 0.85 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:12 AM UTC 25
Peak memory 207648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076189370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3076189370
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.891402559
Short name T1106
Test name
Test status
Simulation time 30781231 ps
CPU time 0.75 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:12 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891402559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.891402559
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1586171289
Short name T1111
Test name
Test status
Simulation time 19793487 ps
CPU time 0.92 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586171289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1586171289
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2390854245
Short name T1114
Test name
Test status
Simulation time 19463012 ps
CPU time 0.93 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390854245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2390854245
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3434181594
Short name T115
Test name
Test status
Simulation time 21008568 ps
CPU time 1.02 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:49 AM UTC 25
Peak memory 210148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434181594 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3434181594
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1701974003
Short name T1014
Test name
Test status
Simulation time 117163528 ps
CPU time 2.21 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701974003 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1701974003
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1665097743
Short name T1008
Test name
Test status
Simulation time 56821411 ps
CPU time 0.84 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 207700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665097743 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1665097743
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3644555858
Short name T72
Test name
Test status
Simulation time 67091398 ps
CPU time 0.86 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:49 AM UTC 25
Peak memory 210272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644555
858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3644555858
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.687661837
Short name T1010
Test name
Test status
Simulation time 22736950 ps
CPU time 1.04 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 208892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687661837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.687661837
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.2335477736
Short name T179
Test name
Test status
Simulation time 45407407 ps
CPU time 0.76 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 207668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335477736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2335477736
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2385673080
Short name T127
Test name
Test status
Simulation time 55432240 ps
CPU time 1 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:49 AM UTC 25
Peak memory 210272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385673080 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.2385673080
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.441624766
Short name T1011
Test name
Test status
Simulation time 198997279 ps
CPU time 1.3 seconds
Started Feb 09 08:32:46 AM UTC 25
Finished Feb 09 08:32:48 AM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441624766 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.441624766
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.1830735140
Short name T1112
Test name
Test status
Simulation time 45595762 ps
CPU time 0.79 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830735140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1830735140
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3438179719
Short name T1110
Test name
Test status
Simulation time 20152406 ps
CPU time 0.76 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438179719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3438179719
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.411764692
Short name T1093
Test name
Test status
Simulation time 22589570 ps
CPU time 0.96 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411764692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.411764692
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.1021271149
Short name T1113
Test name
Test status
Simulation time 19574695 ps
CPU time 0.75 seconds
Started Feb 09 08:33:10 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021271149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.1021271149
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2168010184
Short name T1041
Test name
Test status
Simulation time 82178358 ps
CPU time 0.82 seconds
Started Feb 09 08:33:11 AM UTC 25
Finished Feb 09 08:33:13 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168010184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2168010184
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.3995136185
Short name T1116
Test name
Test status
Simulation time 17522979 ps
CPU time 0.91 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:14 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995136185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3995136185
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.3611155367
Short name T1115
Test name
Test status
Simulation time 55642910 ps
CPU time 0.75 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:14 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611155367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3611155367
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.1277457594
Short name T1119
Test name
Test status
Simulation time 19228494 ps
CPU time 0.95 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:14 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277457594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1277457594
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.529940504
Short name T1118
Test name
Test status
Simulation time 71817908 ps
CPU time 0.91 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:14 AM UTC 25
Peak memory 207764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529940504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.529940504
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2227138310
Short name T1117
Test name
Test status
Simulation time 18189952 ps
CPU time 0.91 seconds
Started Feb 09 08:33:12 AM UTC 25
Finished Feb 09 08:33:14 AM UTC 25
Peak memory 207760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227138310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2227138310
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1259411315
Short name T1016
Test name
Test status
Simulation time 49756345 ps
CPU time 0.98 seconds
Started Feb 09 08:32:49 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 210512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259411
315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.1259411315
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.3187569550
Short name T116
Test name
Test status
Simulation time 96970638 ps
CPU time 0.79 seconds
Started Feb 09 08:32:48 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 208920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187569550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3187569550
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.144634057
Short name T1012
Test name
Test status
Simulation time 61173741 ps
CPU time 0.93 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:50 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144634057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UV
M_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.144634057
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.664386109
Short name T128
Test name
Test status
Simulation time 36732374 ps
CPU time 1.1 seconds
Started Feb 09 08:32:48 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 210208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664386109 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.664386109
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.9985598
Short name T1013
Test name
Test status
Simulation time 33286631 ps
CPU time 1.72 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:50 AM UTC 25
Peak memory 211732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9985598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_
TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.9985598
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2338894985
Short name T68
Test name
Test status
Simulation time 338539227 ps
CPU time 2.14 seconds
Started Feb 09 08:32:47 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 211668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338894985 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.2338894985
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3730505826
Short name T1018
Test name
Test status
Simulation time 39307858 ps
CPU time 0.99 seconds
Started Feb 09 08:32:50 AM UTC 25
Finished Feb 09 08:32:52 AM UTC 25
Peak memory 211736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730505
826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.3730505826
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.3300837960
Short name T117
Test name
Test status
Simulation time 55093383 ps
CPU time 1 seconds
Started Feb 09 08:32:50 AM UTC 25
Finished Feb 09 08:32:52 AM UTC 25
Peak memory 208824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300837960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3300837960
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.2585560144
Short name T1015
Test name
Test status
Simulation time 22304012 ps
CPU time 0.95 seconds
Started Feb 09 08:32:49 AM UTC 25
Finished Feb 09 08:32:51 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585560144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2585560144
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1798972558
Short name T1019
Test name
Test status
Simulation time 92965107 ps
CPU time 1.13 seconds
Started Feb 09 08:32:50 AM UTC 25
Finished Feb 09 08:32:52 AM UTC 25
Peak memory 209804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798972558 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.1798972558
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.2955779142
Short name T1021
Test name
Test status
Simulation time 50869874 ps
CPU time 2.74 seconds
Started Feb 09 08:32:49 AM UTC 25
Finished Feb 09 08:32:53 AM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955779142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2955779142
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2167916975
Short name T69
Test name
Test status
Simulation time 199179152 ps
CPU time 1.79 seconds
Started Feb 09 08:32:49 AM UTC 25
Finished Feb 09 08:32:52 AM UTC 25
Peak memory 211716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167916975 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.2167916975
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1824086164
Short name T1026
Test name
Test status
Simulation time 131649176 ps
CPU time 2.03 seconds
Started Feb 09 08:32:51 AM UTC 25
Finished Feb 09 08:32:54 AM UTC 25
Peak memory 211744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824086
164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1824086164
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.3053680023
Short name T1023
Test name
Test status
Simulation time 22677355 ps
CPU time 0.85 seconds
Started Feb 09 08:32:51 AM UTC 25
Finished Feb 09 08:32:53 AM UTC 25
Peak memory 208860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053680023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3053680023
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.4093471763
Short name T181
Test name
Test status
Simulation time 83411664 ps
CPU time 0.83 seconds
Started Feb 09 08:32:51 AM UTC 25
Finished Feb 09 08:32:53 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093471763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.4093471763
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.4024535115
Short name T1024
Test name
Test status
Simulation time 77092621 ps
CPU time 0.77 seconds
Started Feb 09 08:32:51 AM UTC 25
Finished Feb 09 08:32:53 AM UTC 25
Peak memory 209744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024535115 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.4024535115
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.1355143877
Short name T1022
Test name
Test status
Simulation time 79401406 ps
CPU time 1.69 seconds
Started Feb 09 08:32:50 AM UTC 25
Finished Feb 09 08:32:53 AM UTC 25
Peak memory 211740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355143877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1355143877
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.3246746002
Short name T1020
Test name
Test status
Simulation time 224933645 ps
CPU time 1.48 seconds
Started Feb 09 08:32:50 AM UTC 25
Finished Feb 09 08:32:53 AM UTC 25
Peak memory 211748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246746002 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.3246746002
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3570575938
Short name T1027
Test name
Test status
Simulation time 73785890 ps
CPU time 0.89 seconds
Started Feb 09 08:32:52 AM UTC 25
Finished Feb 09 08:32:54 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570575
938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.3570575938
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.2961650622
Short name T118
Test name
Test status
Simulation time 43098503 ps
CPU time 0.98 seconds
Started Feb 09 08:32:52 AM UTC 25
Finished Feb 09 08:32:54 AM UTC 25
Peak memory 208824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961650622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2961650622
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.2316000504
Short name T1025
Test name
Test status
Simulation time 44352545 ps
CPU time 0.83 seconds
Started Feb 09 08:32:52 AM UTC 25
Finished Feb 09 08:32:54 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316000504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.2316000504
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.4134948188
Short name T1028
Test name
Test status
Simulation time 28769309 ps
CPU time 1.06 seconds
Started Feb 09 08:32:52 AM UTC 25
Finished Feb 09 08:32:55 AM UTC 25
Peak memory 209480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134948188 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.4134948188
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.4159999970
Short name T1029
Test name
Test status
Simulation time 72440567 ps
CPU time 2.6 seconds
Started Feb 09 08:32:51 AM UTC 25
Finished Feb 09 08:32:55 AM UTC 25
Peak memory 211608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159999970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.4159999970
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.80810006
Short name T175
Test name
Test status
Simulation time 196513204 ps
CPU time 1.82 seconds
Started Feb 09 08:32:52 AM UTC 25
Finished Feb 09 08:32:55 AM UTC 25
Peak memory 211792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80810006 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.80810006
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3923083217
Short name T1035
Test name
Test status
Simulation time 88847720 ps
CPU time 1.55 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 211680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923083
217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3923083217
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.2107433739
Short name T1031
Test name
Test status
Simulation time 25892376 ps
CPU time 0.89 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 207636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107433739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2107433739
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.2033284342
Short name T1030
Test name
Test status
Simulation time 33085585 ps
CPU time 0.8 seconds
Started Feb 09 08:32:53 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 207704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033284342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2033284342
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.4039925471
Short name T1034
Test name
Test status
Simulation time 73523307 ps
CPU time 1.24 seconds
Started Feb 09 08:32:54 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 210212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039925471 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.4039925471
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.4258966267
Short name T1036
Test name
Test status
Simulation time 167919649 ps
CPU time 2.81 seconds
Started Feb 09 08:32:52 AM UTC 25
Finished Feb 09 08:32:56 AM UTC 25
Peak memory 211636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258966267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +U
VM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.4258966267
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1298160342
Short name T8
Test name
Test status
Simulation time 50139319 ps
CPU time 1.31 seconds
Started Feb 09 02:03:37 PM UTC 25
Finished Feb 09 02:03:40 PM UTC 25
Peak memory 211136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298160342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.1298160342
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.3957984190
Short name T13
Test name
Test status
Simulation time 76134668 ps
CPU time 0.9 seconds
Started Feb 09 02:03:38 PM UTC 25
Finished Feb 09 02:03:41 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957984190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.3957984190
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2954169156
Short name T6
Test name
Test status
Simulation time 31170936 ps
CPU time 0.75 seconds
Started Feb 09 02:03:37 PM UTC 25
Finished Feb 09 02:03:39 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954169156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.2954169156
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.995767344
Short name T20
Test name
Test status
Simulation time 34324211 ps
CPU time 0.96 seconds
Started Feb 09 02:03:38 PM UTC 25
Finished Feb 09 02:03:41 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995767344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.995767344
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.1214510512
Short name T10
Test name
Test status
Simulation time 90423524 ps
CPU time 0.9 seconds
Started Feb 09 02:03:38 PM UTC 25
Finished Feb 09 02:03:41 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214510512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.1214510512
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.4063869971
Short name T4
Test name
Test status
Simulation time 105708401 ps
CPU time 1.13 seconds
Started Feb 09 02:03:36 PM UTC 25
Finished Feb 09 02:03:38 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063869971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.4063869971
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2846809536
Short name T2
Test name
Test status
Simulation time 56946259 ps
CPU time 1.12 seconds
Started Feb 09 02:03:35 PM UTC 25
Finished Feb 09 02:03:37 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846809536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2846809536
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2332610423
Short name T21
Test name
Test status
Simulation time 435130942 ps
CPU time 1.66 seconds
Started Feb 09 02:03:40 PM UTC 25
Finished Feb 09 02:03:43 PM UTC 25
Peak memory 236992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332610423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2332610423
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2611703877
Short name T9
Test name
Test status
Simulation time 68877923 ps
CPU time 1.25 seconds
Started Feb 09 02:03:37 PM UTC 25
Finished Feb 09 02:03:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611703877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.2611703877
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1123430134
Short name T14
Test name
Test status
Simulation time 946383901 ps
CPU time 2.82 seconds
Started Feb 09 02:03:37 PM UTC 25
Finished Feb 09 02:03:41 PM UTC 25
Peak memory 211396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123430134 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1123430134
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.532732470
Short name T38
Test name
Test status
Simulation time 1302657691 ps
CPU time 2.79 seconds
Started Feb 09 02:03:37 PM UTC 25
Finished Feb 09 02:03:41 PM UTC 25
Peak memory 211364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532732470 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.532732470
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2665365610
Short name T7
Test name
Test status
Simulation time 223308536 ps
CPU time 1.13 seconds
Started Feb 09 02:03:37 PM UTC 25
Finished Feb 09 02:03:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665365610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2665365610
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.3538623448
Short name T1
Test name
Test status
Simulation time 31037247 ps
CPU time 0.88 seconds
Started Feb 09 02:03:35 PM UTC 25
Finished Feb 09 02:03:37 PM UTC 25
Peak memory 210436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538623448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3538623448
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.2524771266
Short name T24
Test name
Test status
Simulation time 5892474166 ps
CPU time 17.84 seconds
Started Feb 09 02:03:40 PM UTC 25
Finished Feb 09 02:03:59 PM UTC 25
Peak memory 211980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2524771266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_
reset.2524771266
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3922965805
Short name T3
Test name
Test status
Simulation time 62772849 ps
CPU time 0.91 seconds
Started Feb 09 02:03:36 PM UTC 25
Finished Feb 09 02:03:38 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922965805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.3922965805
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1758678613
Short name T16
Test name
Test status
Simulation time 56912031 ps
CPU time 1.01 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:44 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758678613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1758678613
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.3382634264
Short name T28
Test name
Test status
Simulation time 69069805 ps
CPU time 0.88 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:45 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382634264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.3382634264
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1167997986
Short name T12
Test name
Test status
Simulation time 30847823 ps
CPU time 0.82 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:45 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167997986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.1167997986
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.3002474935
Short name T157
Test name
Test status
Simulation time 827519438 ps
CPU time 1.72 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:46 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002474935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.3002474935
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2571620752
Short name T37
Test name
Test status
Simulation time 39486365 ps
CPU time 0.87 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:45 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571620752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2571620752
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.4274698941
Short name T44
Test name
Test status
Simulation time 112080660 ps
CPU time 0.83 seconds
Started Feb 09 02:03:44 PM UTC 25
Finished Feb 09 02:03:46 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274698941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.4274698941
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3822793692
Short name T34
Test name
Test status
Simulation time 200307049 ps
CPU time 1.18 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:44 PM UTC 25
Peak memory 208396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822793692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.3822793692
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.274360160
Short name T35
Test name
Test status
Simulation time 44638761 ps
CPU time 1.22 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:44 PM UTC 25
Peak memory 210952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274360160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.274360160
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.4201510042
Short name T39
Test name
Test status
Simulation time 124134458 ps
CPU time 1.28 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:46 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201510042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.4201510042
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3523396928
Short name T60
Test name
Test status
Simulation time 141197827 ps
CPU time 1.17 seconds
Started Feb 09 02:03:43 PM UTC 25
Finished Feb 09 02:03:45 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523396928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.3523396928
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1207540554
Short name T172
Test name
Test status
Simulation time 946125705 ps
CPU time 5.24 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:48 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207540554 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1207540554
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.30362371
Short name T36
Test name
Test status
Simulation time 90020352 ps
CPU time 1.3 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:44 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30362371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.30362371
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.1525466466
Short name T78
Test name
Test status
Simulation time 62570939 ps
CPU time 0.93 seconds
Started Feb 09 02:03:40 PM UTC 25
Finished Feb 09 02:03:42 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525466466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1525466466
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.464173947
Short name T27
Test name
Test status
Simulation time 73747382 ps
CPU time 0.64 seconds
Started Feb 09 02:03:44 PM UTC 25
Finished Feb 09 02:03:46 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464173947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.464173947
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1334228834
Short name T32
Test name
Test status
Simulation time 148935955 ps
CPU time 0.87 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:43 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334228834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1334228834
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.910479121
Short name T33
Test name
Test status
Simulation time 184649477 ps
CPU time 0.99 seconds
Started Feb 09 02:03:41 PM UTC 25
Finished Feb 09 02:03:44 PM UTC 25
Peak memory 210772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910479121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.910479121
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.2528860918
Short name T279
Test name
Test status
Simulation time 43186200 ps
CPU time 1.16 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:28 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528860918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2528860918
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.3683823508
Short name T287
Test name
Test status
Simulation time 72210708 ps
CPU time 0.94 seconds
Started Feb 09 02:04:26 PM UTC 25
Finished Feb 09 02:04:29 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683823508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.3683823508
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1207130785
Short name T276
Test name
Test status
Simulation time 42896196 ps
CPU time 0.79 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:27 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207130785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.1207130785
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.271598810
Short name T283
Test name
Test status
Simulation time 710551505 ps
CPU time 1.54 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:28 PM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271598810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.271598810
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3880096735
Short name T277
Test name
Test status
Simulation time 92706003 ps
CPU time 0.9 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:27 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880096735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3880096735
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.2438587655
Short name T278
Test name
Test status
Simulation time 52322042 ps
CPU time 0.91 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:27 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438587655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2438587655
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.835487215
Short name T288
Test name
Test status
Simulation time 72427114 ps
CPU time 1 seconds
Started Feb 09 02:04:27 PM UTC 25
Finished Feb 09 02:04:29 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835487215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.835487215
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.81219247
Short name T275
Test name
Test status
Simulation time 78645188 ps
CPU time 1.26 seconds
Started Feb 09 02:04:23 PM UTC 25
Finished Feb 09 02:04:25 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81219247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.81219247
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.2961211113
Short name T274
Test name
Test status
Simulation time 57903699 ps
CPU time 0.87 seconds
Started Feb 09 02:04:23 PM UTC 25
Finished Feb 09 02:04:25 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961211113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2961211113
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.1231288854
Short name T289
Test name
Test status
Simulation time 115731252 ps
CPU time 1.55 seconds
Started Feb 09 02:04:26 PM UTC 25
Finished Feb 09 02:04:30 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231288854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1231288854
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.784336481
Short name T284
Test name
Test status
Simulation time 343981415 ps
CPU time 2.03 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:29 PM UTC 25
Peak memory 210944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784336481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.784336481
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2097353980
Short name T285
Test name
Test status
Simulation time 1829096598 ps
CPU time 2.27 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:29 PM UTC 25
Peak memory 211348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097353980 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2097353980
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4058498886
Short name T286
Test name
Test status
Simulation time 1035124984 ps
CPU time 2.75 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:29 PM UTC 25
Peak memory 211312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058498886 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4058498886
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1114328801
Short name T281
Test name
Test status
Simulation time 65199743 ps
CPU time 1.26 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:28 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114328801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1114328801
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.1499743193
Short name T106
Test name
Test status
Simulation time 40512539 ps
CPU time 0.96 seconds
Started Feb 09 02:04:23 PM UTC 25
Finished Feb 09 02:04:25 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499743193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.1499743193
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.1274023056
Short name T290
Test name
Test status
Simulation time 862886364 ps
CPU time 1.98 seconds
Started Feb 09 02:04:27 PM UTC 25
Finished Feb 09 02:04:30 PM UTC 25
Peak memory 210888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274023056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.1274023056
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3676407940
Short name T50
Test name
Test status
Simulation time 20099533332 ps
CPU time 10.89 seconds
Started Feb 09 02:04:27 PM UTC 25
Finished Feb 09 02:04:39 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3676407940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand
_reset.3676407940
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.53891081
Short name T280
Test name
Test status
Simulation time 85319930 ps
CPU time 1.31 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:28 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53891081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.53891081
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3779959570
Short name T282
Test name
Test status
Simulation time 243968608 ps
CPU time 1.7 seconds
Started Feb 09 02:04:25 PM UTC 25
Finished Feb 09 02:04:28 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779959570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3779959570
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.607671729
Short name T298
Test name
Test status
Simulation time 44707715 ps
CPU time 1.02 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 208516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607671729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.607671729
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.1423459054
Short name T193
Test name
Test status
Simulation time 93677239 ps
CPU time 1.04 seconds
Started Feb 09 02:04:32 PM UTC 25
Finished Feb 09 02:04:34 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423459054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.1423459054
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.885499762
Short name T299
Test name
Test status
Simulation time 29292845 ps
CPU time 0.99 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885499762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.885499762
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.589858643
Short name T305
Test name
Test status
Simulation time 158453178 ps
CPU time 1.33 seconds
Started Feb 09 02:04:32 PM UTC 25
Finished Feb 09 02:04:35 PM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589858643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.589858643
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.658573613
Short name T304
Test name
Test status
Simulation time 156412927 ps
CPU time 0.89 seconds
Started Feb 09 02:04:32 PM UTC 25
Finished Feb 09 02:04:34 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658573613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.658573613
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.395198658
Short name T303
Test name
Test status
Simulation time 41819478 ps
CPU time 0.9 seconds
Started Feb 09 02:04:32 PM UTC 25
Finished Feb 09 02:04:34 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395198658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.395198658
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.2817467449
Short name T308
Test name
Test status
Simulation time 56215292 ps
CPU time 0.82 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:37 PM UTC 25
Peak memory 210912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817467449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.2817467449
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.4005685992
Short name T295
Test name
Test status
Simulation time 176966111 ps
CPU time 1.14 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005685992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.4005685992
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.2026572158
Short name T294
Test name
Test status
Simulation time 72813957 ps
CPU time 1.01 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 210580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026572158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2026572158
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.180011113
Short name T306
Test name
Test status
Simulation time 143979373 ps
CPU time 1.15 seconds
Started Feb 09 02:04:32 PM UTC 25
Finished Feb 09 02:04:35 PM UTC 25
Peak memory 220148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180011113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.180011113
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.4058232608
Short name T301
Test name
Test status
Simulation time 192822577 ps
CPU time 1.49 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:34 PM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058232608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.4058232608
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.574536463
Short name T302
Test name
Test status
Simulation time 994930129 ps
CPU time 2.21 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:34 PM UTC 25
Peak memory 211540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574536463 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.574536463
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.891826092
Short name T307
Test name
Test status
Simulation time 925232072 ps
CPU time 4.38 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:36 PM UTC 25
Peak memory 211696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891826092 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.891826092
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.630509089
Short name T300
Test name
Test status
Simulation time 94343197 ps
CPU time 1.39 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630509089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.630509089
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.1461507306
Short name T293
Test name
Test status
Simulation time 58689440 ps
CPU time 0.91 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:32 PM UTC 25
Peak memory 208192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461507306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.1461507306
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2930332552
Short name T323
Test name
Test status
Simulation time 1917605601 ps
CPU time 4.28 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930332552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.2930332552
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2493515095
Short name T378
Test name
Test status
Simulation time 15033170181 ps
CPU time 20.89 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:57 PM UTC 25
Peak memory 211320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2493515095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand
_reset.2493515095
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1676898785
Short name T296
Test name
Test status
Simulation time 236704449 ps
CPU time 1.16 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676898785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1676898785
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2156770822
Short name T297
Test name
Test status
Simulation time 323929903 ps
CPU time 1.02 seconds
Started Feb 09 02:04:30 PM UTC 25
Finished Feb 09 02:04:33 PM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156770822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.2156770822
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.2246672861
Short name T314
Test name
Test status
Simulation time 33053645 ps
CPU time 1.45 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 211208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246672861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.2246672861
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.1070299593
Short name T320
Test name
Test status
Simulation time 58432786 ps
CPU time 1.24 seconds
Started Feb 09 02:04:37 PM UTC 25
Finished Feb 09 02:04:40 PM UTC 25
Peak memory 210720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070299593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.1070299593
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.4156770434
Short name T310
Test name
Test status
Simulation time 34146884 ps
CPU time 0.89 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156770434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.4156770434
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.1035798008
Short name T322
Test name
Test status
Simulation time 166554155 ps
CPU time 1.71 seconds
Started Feb 09 02:04:37 PM UTC 25
Finished Feb 09 02:04:40 PM UTC 25
Peak memory 208236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035798008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1035798008
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.485645718
Short name T317
Test name
Test status
Simulation time 86240537 ps
CPU time 0.86 seconds
Started Feb 09 02:04:37 PM UTC 25
Finished Feb 09 02:04:39 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485645718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.485645718
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.2328404246
Short name T318
Test name
Test status
Simulation time 33914476 ps
CPU time 1.02 seconds
Started Feb 09 02:04:37 PM UTC 25
Finished Feb 09 02:04:39 PM UTC 25
Peak memory 208104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328404246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.2328404246
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.4177040381
Short name T324
Test name
Test status
Simulation time 40237154 ps
CPU time 0.91 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177040381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.4177040381
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.3100601517
Short name T311
Test name
Test status
Simulation time 48640866 ps
CPU time 1.15 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100601517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.3100601517
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2960788541
Short name T309
Test name
Test status
Simulation time 124283574 ps
CPU time 1.2 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 210624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960788541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2960788541
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.737808002
Short name T328
Test name
Test status
Simulation time 179354911 ps
CPU time 1.23 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 220140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737808002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.737808002
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1762283329
Short name T316
Test name
Test status
Simulation time 245056495 ps
CPU time 2.02 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:39 PM UTC 25
Peak memory 211204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762283329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.1762283329
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2159777249
Short name T321
Test name
Test status
Simulation time 1017066973 ps
CPU time 3.22 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:40 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159777249 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2159777249
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1072461893
Short name T319
Test name
Test status
Simulation time 1097934487 ps
CPU time 2.88 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:39 PM UTC 25
Peak memory 211524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072461893 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1072461893
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2849856346
Short name T312
Test name
Test status
Simulation time 100457967 ps
CPU time 0.97 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849856346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2849856346
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.133046457
Short name T292
Test name
Test status
Simulation time 60538579 ps
CPU time 0.9 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:37 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133046457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.133046457
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.1551948721
Short name T332
Test name
Test status
Simulation time 935524420 ps
CPU time 4.11 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:44 PM UTC 25
Peak memory 211304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551948721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.1551948721
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1926672760
Short name T384
Test name
Test status
Simulation time 16719791902 ps
CPU time 17.97 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:58 PM UTC 25
Peak memory 211608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1926672760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand
_reset.1926672760
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.916245121
Short name T313
Test name
Test status
Simulation time 255380072 ps
CPU time 1.32 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916245121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.916245121
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.3269399942
Short name T315
Test name
Test status
Simulation time 403727218 ps
CPU time 1.65 seconds
Started Feb 09 02:04:35 PM UTC 25
Finished Feb 09 02:04:38 PM UTC 25
Peak memory 210516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269399942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3269399942
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.3367343897
Short name T331
Test name
Test status
Simulation time 37890826 ps
CPU time 1.07 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:44 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367343897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.3367343897
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.2613095855
Short name T337
Test name
Test status
Simulation time 100213292 ps
CPU time 1.07 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:45 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613095855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.2613095855
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.892359762
Short name T333
Test name
Test status
Simulation time 37158058 ps
CPU time 0.88 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:44 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892359762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.892359762
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.37150356
Short name T341
Test name
Test status
Simulation time 754352746 ps
CPU time 1.69 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:45 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37150356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esca
lation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.37150356
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2400414496
Short name T334
Test name
Test status
Simulation time 23312491 ps
CPU time 0.95 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:44 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400414496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2400414496
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.2101962821
Short name T336
Test name
Test status
Simulation time 37942542 ps
CPU time 0.98 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:44 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101962821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.2101962821
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.1623068454
Short name T338
Test name
Test status
Simulation time 53729484 ps
CPU time 0.93 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:45 PM UTC 25
Peak memory 211008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623068454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.1623068454
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.2486059227
Short name T325
Test name
Test status
Simulation time 76186873 ps
CPU time 0.97 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486059227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.2486059227
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.483919982
Short name T329
Test name
Test status
Simulation time 167984467 ps
CPU time 1.17 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 210836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483919982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.483919982
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.2573480263
Short name T340
Test name
Test status
Simulation time 89631081 ps
CPU time 1.27 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:45 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573480263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2573480263
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3842700625
Short name T339
Test name
Test status
Simulation time 84585864 ps
CPU time 1.37 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:45 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842700625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.3842700625
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1034721236
Short name T343
Test name
Test status
Simulation time 869779677 ps
CPU time 3.37 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:47 PM UTC 25
Peak memory 211312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034721236 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1034721236
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3577015459
Short name T342
Test name
Test status
Simulation time 1407371422 ps
CPU time 2.64 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:46 PM UTC 25
Peak memory 211312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577015459 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3577015459
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3195044083
Short name T335
Test name
Test status
Simulation time 50737329 ps
CPU time 1.15 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:44 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195044083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3195044083
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.177118625
Short name T326
Test name
Test status
Simulation time 31257361 ps
CPU time 1.03 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177118625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.177118625
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.1846059245
Short name T355
Test name
Test status
Simulation time 1029122492 ps
CPU time 4.42 seconds
Started Feb 09 02:04:44 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 211368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846059245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.1846059245
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.4258572415
Short name T381
Test name
Test status
Simulation time 5042045658 ps
CPU time 13.75 seconds
Started Feb 09 02:04:42 PM UTC 25
Finished Feb 09 02:04:58 PM UTC 25
Peak memory 211740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4258572415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand
_reset.4258572415
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.826522319
Short name T330
Test name
Test status
Simulation time 205303992 ps
CPU time 1.36 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:42 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826522319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.826522319
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.1877231419
Short name T327
Test name
Test status
Simulation time 150640211 ps
CPU time 0.91 seconds
Started Feb 09 02:04:39 PM UTC 25
Finished Feb 09 02:04:41 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877231419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.1877231419
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.737041100
Short name T354
Test name
Test status
Simulation time 40086296 ps
CPU time 1.23 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737041100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.737041100
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.4151392616
Short name T360
Test name
Test status
Simulation time 48268856 ps
CPU time 1.16 seconds
Started Feb 09 02:04:49 PM UTC 25
Finished Feb 09 02:04:52 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151392616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.4151392616
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1033597261
Short name T349
Test name
Test status
Simulation time 31955713 ps
CPU time 0.88 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 208188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033597261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.1033597261
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.2948482501
Short name T356
Test name
Test status
Simulation time 312232627 ps
CPU time 1.4 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948482501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2948482501
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.1620723045
Short name T350
Test name
Test status
Simulation time 33449522 ps
CPU time 0.84 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620723045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1620723045
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.3118279937
Short name T348
Test name
Test status
Simulation time 126566997 ps
CPU time 0.83 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118279937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3118279937
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.347307804
Short name T359
Test name
Test status
Simulation time 43012028 ps
CPU time 1.12 seconds
Started Feb 09 02:04:49 PM UTC 25
Finished Feb 09 02:04:52 PM UTC 25
Peak memory 210152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347307804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.347307804
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.3811999646
Short name T346
Test name
Test status
Simulation time 310029781 ps
CPU time 1.4 seconds
Started Feb 09 02:04:44 PM UTC 25
Finished Feb 09 02:04:47 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811999646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.3811999646
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.3530730831
Short name T345
Test name
Test status
Simulation time 71674769 ps
CPU time 1.26 seconds
Started Feb 09 02:04:44 PM UTC 25
Finished Feb 09 02:04:47 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530730831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3530730831
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.3917337431
Short name T361
Test name
Test status
Simulation time 108159920 ps
CPU time 1.32 seconds
Started Feb 09 02:04:49 PM UTC 25
Finished Feb 09 02:04:52 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917337431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3917337431
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3670696782
Short name T352
Test name
Test status
Simulation time 168770897 ps
CPU time 1.19 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670696782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.3670696782
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1475689184
Short name T357
Test name
Test status
Simulation time 1104913524 ps
CPU time 2.53 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:51 PM UTC 25
Peak memory 210664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475689184 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1475689184
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3056146118
Short name T362
Test name
Test status
Simulation time 810185242 ps
CPU time 3.68 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:52 PM UTC 25
Peak memory 211312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056146118 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3056146118
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.4114899545
Short name T351
Test name
Test status
Simulation time 101986600 ps
CPU time 1.17 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114899545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.4114899545
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.291975239
Short name T344
Test name
Test status
Simulation time 33361681 ps
CPU time 0.99 seconds
Started Feb 09 02:04:44 PM UTC 25
Finished Feb 09 02:04:47 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291975239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.291975239
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.2652826206
Short name T365
Test name
Test status
Simulation time 2140578350 ps
CPU time 3.57 seconds
Started Feb 09 02:04:49 PM UTC 25
Finished Feb 09 02:04:54 PM UTC 25
Peak memory 211368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652826206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2652826206
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1626081681
Short name T426
Test name
Test status
Simulation time 10670300420 ps
CPU time 22.72 seconds
Started Feb 09 02:04:49 PM UTC 25
Finished Feb 09 02:05:13 PM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1626081681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand
_reset.1626081681
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2106347887
Short name T347
Test name
Test status
Simulation time 25349968 ps
CPU time 0.86 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:49 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106347887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2106347887
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.2375139508
Short name T353
Test name
Test status
Simulation time 416602372 ps
CPU time 1.24 seconds
Started Feb 09 02:04:47 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375139508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2375139508
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.1126349509
Short name T372
Test name
Test status
Simulation time 156697538 ps
CPU time 1.08 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126349509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1126349509
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.3811602557
Short name T189
Test name
Test status
Simulation time 86426168 ps
CPU time 0.89 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 210676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811602557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.3811602557
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3802115467
Short name T368
Test name
Test status
Simulation time 40146440 ps
CPU time 0.85 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802115467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.3802115467
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.2011598679
Short name T376
Test name
Test status
Simulation time 601725553 ps
CPU time 1.33 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:57 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011598679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2011598679
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.548360129
Short name T371
Test name
Test status
Simulation time 34198631 ps
CPU time 0.83 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548360129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.548360129
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.215712055
Short name T370
Test name
Test status
Simulation time 46129420 ps
CPU time 0.83 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 206404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215712055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.215712055
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.551679016
Short name T375
Test name
Test status
Simulation time 43871330 ps
CPU time 1.06 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:57 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551679016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.551679016
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.3110731248
Short name T364
Test name
Test status
Simulation time 253338914 ps
CPU time 1.15 seconds
Started Feb 09 02:04:50 PM UTC 25
Finished Feb 09 02:04:53 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110731248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.3110731248
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3011748941
Short name T363
Test name
Test status
Simulation time 79064199 ps
CPU time 0.92 seconds
Started Feb 09 02:04:50 PM UTC 25
Finished Feb 09 02:04:53 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011748941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3011748941
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.1592594718
Short name T377
Test name
Test status
Simulation time 95758017 ps
CPU time 1.51 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:57 PM UTC 25
Peak memory 220172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592594718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1592594718
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.1184378481
Short name T367
Test name
Test status
Simulation time 261078322 ps
CPU time 2.1 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:57 PM UTC 25
Peak memory 210948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184378481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.1184378481
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.662140100
Short name T379
Test name
Test status
Simulation time 1138381137 ps
CPU time 2.28 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:57 PM UTC 25
Peak memory 211348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662140100 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.662140100
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2231778674
Short name T385
Test name
Test status
Simulation time 983949646 ps
CPU time 3.92 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:59 PM UTC 25
Peak memory 211360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231778674 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2231778674
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4001804411
Short name T373
Test name
Test status
Simulation time 92424195 ps
CPU time 1.18 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001804411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4001804411
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.1176687581
Short name T358
Test name
Test status
Simulation time 35302112 ps
CPU time 0.93 seconds
Started Feb 09 02:04:49 PM UTC 25
Finished Feb 09 02:04:51 PM UTC 25
Peak memory 210916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176687581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1176687581
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.411470988
Short name T389
Test name
Test status
Simulation time 1643197159 ps
CPU time 5.5 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 211436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411470988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.411470988
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3349209177
Short name T442
Test name
Test status
Simulation time 8109732759 ps
CPU time 18.59 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 211932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3349209177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand
_reset.3349209177
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.454703561
Short name T369
Test name
Test status
Simulation time 204908903 ps
CPU time 1.02 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454703561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.454703561
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1085256096
Short name T366
Test name
Test status
Simulation time 156770803 ps
CPU time 0.85 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 211196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085256096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.1085256096
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.312501009
Short name T395
Test name
Test status
Simulation time 34787130 ps
CPU time 1.54 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:02 PM UTC 25
Peak memory 211188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312501009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.312501009
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.994524396
Short name T390
Test name
Test status
Simulation time 114374611 ps
CPU time 0.86 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994524396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.994524396
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.660557172
Short name T386
Test name
Test status
Simulation time 31374383 ps
CPU time 0.64 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660557172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.660557172
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.470398186
Short name T397
Test name
Test status
Simulation time 328881912 ps
CPU time 1.66 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:02 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470398186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.470398186
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.1030457918
Short name T388
Test name
Test status
Simulation time 45286589 ps
CPU time 0.76 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030457918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1030457918
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.1487411240
Short name T387
Test name
Test status
Simulation time 56473774 ps
CPU time 0.72 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 208428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487411240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.1487411240
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1404841174
Short name T391
Test name
Test status
Simulation time 40361891 ps
CPU time 1.01 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 211132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404841174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.1404841174
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.3718790910
Short name T383
Test name
Test status
Simulation time 403358575 ps
CPU time 1.15 seconds
Started Feb 09 02:04:56 PM UTC 25
Finished Feb 09 02:04:58 PM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718790910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.3718790910
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.3110146528
Short name T380
Test name
Test status
Simulation time 43492183 ps
CPU time 0.97 seconds
Started Feb 09 02:04:56 PM UTC 25
Finished Feb 09 02:04:58 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110146528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3110146528
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.937638298
Short name T394
Test name
Test status
Simulation time 112869226 ps
CPU time 1.19 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 220200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937638298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.937638298
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.2385647054
Short name T392
Test name
Test status
Simulation time 70458111 ps
CPU time 1.17 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385647054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.2385647054
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.689923134
Short name T398
Test name
Test status
Simulation time 1279404414 ps
CPU time 2.45 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:02 PM UTC 25
Peak memory 211476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689923134 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.689923134
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.993877432
Short name T399
Test name
Test status
Simulation time 824082582 ps
CPU time 3.07 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:03 PM UTC 25
Peak memory 211248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993877432 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.993877432
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2557422908
Short name T393
Test name
Test status
Simulation time 72184670 ps
CPU time 1.31 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:01 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557422908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2557422908
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3810559476
Short name T374
Test name
Test status
Simulation time 29918472 ps
CPU time 0.73 seconds
Started Feb 09 02:04:54 PM UTC 25
Finished Feb 09 02:04:56 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810559476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3810559476
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.2228453685
Short name T400
Test name
Test status
Simulation time 6804870686 ps
CPU time 4.7 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:05 PM UTC 25
Peak memory 211872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228453685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.2228453685
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.335931673
Short name T471
Test name
Test status
Simulation time 11587511082 ps
CPU time 21.46 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:22 PM UTC 25
Peak memory 211916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=335931673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_
reset.335931673
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2160377085
Short name T382
Test name
Test status
Simulation time 220064748 ps
CPU time 0.97 seconds
Started Feb 09 02:04:56 PM UTC 25
Finished Feb 09 02:04:58 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160377085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2160377085
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.3024670157
Short name T396
Test name
Test status
Simulation time 292725317 ps
CPU time 1.85 seconds
Started Feb 09 02:04:59 PM UTC 25
Finished Feb 09 02:05:02 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024670157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3024670157
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.215126957
Short name T403
Test name
Test status
Simulation time 70421526 ps
CPU time 0.98 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 211136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215126957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.215126957
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1771903848
Short name T414
Test name
Test status
Simulation time 76831413 ps
CPU time 1.15 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 210720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771903848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.1771903848
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2253181345
Short name T402
Test name
Test status
Simulation time 38963703 ps
CPU time 0.66 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253181345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.2253181345
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.2020602353
Short name T413
Test name
Test status
Simulation time 316796409 ps
CPU time 1.12 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020602353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.2020602353
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.3830138497
Short name T409
Test name
Test status
Simulation time 41210581 ps
CPU time 0.86 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830138497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3830138497
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.1916839178
Short name T406
Test name
Test status
Simulation time 68553006 ps
CPU time 0.79 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916839178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1916839178
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.2069259516
Short name T412
Test name
Test status
Simulation time 51564754 ps
CPU time 0.92 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 211004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069259516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.2069259516
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.614618049
Short name T410
Test name
Test status
Simulation time 309382520 ps
CPU time 1.33 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614618049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.614618049
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.257358374
Short name T408
Test name
Test status
Simulation time 69968014 ps
CPU time 1.35 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 210688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257358374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.257358374
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2182624199
Short name T415
Test name
Test status
Simulation time 109636774 ps
CPU time 1.39 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:07 PM UTC 25
Peak memory 220104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182624199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2182624199
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3129841121
Short name T411
Test name
Test status
Simulation time 33303865 ps
CPU time 1.06 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129841121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.3129841121
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2403689510
Short name T416
Test name
Test status
Simulation time 823282264 ps
CPU time 3.03 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:08 PM UTC 25
Peak memory 211332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403689510 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2403689510
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1113025797
Short name T417
Test name
Test status
Simulation time 785800426 ps
CPU time 3.21 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:08 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113025797 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1113025797
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3164374903
Short name T404
Test name
Test status
Simulation time 109539657 ps
CPU time 0.88 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164374903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3164374903
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.180120587
Short name T401
Test name
Test status
Simulation time 65969422 ps
CPU time 0.69 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:05 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180120587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.180120587
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.1706926629
Short name T433
Test name
Test status
Simulation time 1844530497 ps
CPU time 6.29 seconds
Started Feb 09 02:05:06 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706926629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.1706926629
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2823841600
Short name T498
Test name
Test status
Simulation time 12034847846 ps
CPU time 25.43 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:31 PM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2823841600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand
_reset.2823841600
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.1515260433
Short name T405
Test name
Test status
Simulation time 351693116 ps
CPU time 1.12 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515260433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.1515260433
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.179338992
Short name T407
Test name
Test status
Simulation time 79853462 ps
CPU time 1.15 seconds
Started Feb 09 02:05:04 PM UTC 25
Finished Feb 09 02:05:06 PM UTC 25
Peak memory 210712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179338992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.179338992
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.2358573805
Short name T424
Test name
Test status
Simulation time 72292706 ps
CPU time 0.98 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:13 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358573805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.2358573805
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.2437167350
Short name T436
Test name
Test status
Simulation time 52551068 ps
CPU time 1.23 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437167350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.2437167350
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.922394227
Short name T423
Test name
Test status
Simulation time 32076778 ps
CPU time 0.61 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:13 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922394227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.922394227
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.3757606938
Short name T435
Test name
Test status
Simulation time 576087860 ps
CPU time 1.3 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757606938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3757606938
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.2325287652
Short name T425
Test name
Test status
Simulation time 44813831 ps
CPU time 0.85 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:13 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325287652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2325287652
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.148161837
Short name T429
Test name
Test status
Simulation time 35543926 ps
CPU time 0.98 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148161837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.148161837
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.276899999
Short name T428
Test name
Test status
Simulation time 54530434 ps
CPU time 0.73 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:13 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276899999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.276899999
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.191942600
Short name T422
Test name
Test status
Simulation time 230870869 ps
CPU time 1.7 seconds
Started Feb 09 02:05:06 PM UTC 25
Finished Feb 09 02:05:09 PM UTC 25
Peak memory 211196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191942600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.191942600
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.4291095220
Short name T419
Test name
Test status
Simulation time 46012297 ps
CPU time 0.89 seconds
Started Feb 09 02:05:06 PM UTC 25
Finished Feb 09 02:05:08 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291095220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.4291095220
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.2064649293
Short name T440
Test name
Test status
Simulation time 118202727 ps
CPU time 1.34 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064649293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2064649293
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3079983851
Short name T432
Test name
Test status
Simulation time 112488150 ps
CPU time 1.21 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079983851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.3079983851
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2350969955
Short name T444
Test name
Test status
Simulation time 745932512 ps
CPU time 3.08 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:15 PM UTC 25
Peak memory 211288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350969955 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2350969955
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2218883489
Short name T443
Test name
Test status
Simulation time 1190795320 ps
CPU time 2.39 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:15 PM UTC 25
Peak memory 211132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218883489 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2218883489
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.4056390338
Short name T431
Test name
Test status
Simulation time 99882153 ps
CPU time 1.31 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056390338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.4056390338
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.4052851656
Short name T418
Test name
Test status
Simulation time 32944930 ps
CPU time 0.9 seconds
Started Feb 09 02:05:06 PM UTC 25
Finished Feb 09 02:05:08 PM UTC 25
Peak memory 208452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052851656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.4052851656
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.173184848
Short name T445
Test name
Test status
Simulation time 559293005 ps
CPU time 2.72 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:16 PM UTC 25
Peak memory 211212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173184848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.173184848
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.1316708964
Short name T84
Test name
Test status
Simulation time 4635872408 ps
CPU time 10.67 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:24 PM UTC 25
Peak memory 211868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1316708964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand
_reset.1316708964
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.3928415142
Short name T420
Test name
Test status
Simulation time 370280221 ps
CPU time 1.04 seconds
Started Feb 09 02:05:06 PM UTC 25
Finished Feb 09 02:05:09 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928415142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.3928415142
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.2246045182
Short name T421
Test name
Test status
Simulation time 296999879 ps
CPU time 1.39 seconds
Started Feb 09 02:05:06 PM UTC 25
Finished Feb 09 02:05:09 PM UTC 25
Peak memory 210836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246045182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.2246045182
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3158032088
Short name T438
Test name
Test status
Simulation time 36786788 ps
CPU time 0.98 seconds
Started Feb 09 02:05:12 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158032088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3158032088
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.1198710189
Short name T456
Test name
Test status
Simulation time 66856584 ps
CPU time 1.05 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198710189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.1198710189
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.484884286
Short name T448
Test name
Test status
Simulation time 41124911 ps
CPU time 0.73 seconds
Started Feb 09 02:05:17 PM UTC 25
Finished Feb 09 02:05:19 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484884286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.484884286
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.3159487380
Short name T461
Test name
Test status
Simulation time 165374974 ps
CPU time 1.19 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159487380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3159487380
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.36781011
Short name T455
Test name
Test status
Simulation time 57576874 ps
CPU time 0.84 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36781011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.36781011
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.767375637
Short name T452
Test name
Test status
Simulation time 83242556 ps
CPU time 0.7 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767375637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.767375637
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.2283156640
Short name T453
Test name
Test status
Simulation time 107988505 ps
CPU time 0.74 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283156640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.2283156640
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.3535803350
Short name T439
Test name
Test status
Simulation time 200805706 ps
CPU time 1.11 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535803350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.3535803350
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.685750485
Short name T434
Test name
Test status
Simulation time 116918957 ps
CPU time 0.95 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685750485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.685750485
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.3670922580
Short name T463
Test name
Test status
Simulation time 90793267 ps
CPU time 1.22 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670922580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3670922580
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1724373723
Short name T450
Test name
Test status
Simulation time 271903232 ps
CPU time 0.92 seconds
Started Feb 09 02:05:17 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 211140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724373723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.1724373723
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2802747633
Short name T446
Test name
Test status
Simulation time 2209852372 ps
CPU time 2.04 seconds
Started Feb 09 02:05:13 PM UTC 25
Finished Feb 09 02:05:16 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802747633 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2802747633
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1414456660
Short name T447
Test name
Test status
Simulation time 1363085518 ps
CPU time 2.23 seconds
Started Feb 09 02:05:13 PM UTC 25
Finished Feb 09 02:05:16 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414456660 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1414456660
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.949097506
Short name T462
Test name
Test status
Simulation time 72070143 ps
CPU time 1.34 seconds
Started Feb 09 02:05:17 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949097506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.949097506
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.2485545503
Short name T430
Test name
Test status
Simulation time 51039470 ps
CPU time 0.81 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485545503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.2485545503
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.3816402705
Short name T460
Test name
Test status
Simulation time 367912310 ps
CPU time 1.07 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816402705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3816402705
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.158903882
Short name T522
Test name
Test status
Simulation time 14956047829 ps
CPU time 17.53 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:37 PM UTC 25
Peak memory 211592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=158903882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_
reset.158903882
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.1845262433
Short name T441
Test name
Test status
Simulation time 235130840 ps
CPU time 1.1 seconds
Started Feb 09 02:05:11 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845262433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.1845262433
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.1520849014
Short name T437
Test name
Test status
Simulation time 180816522 ps
CPU time 0.95 seconds
Started Feb 09 02:05:12 PM UTC 25
Finished Feb 09 02:05:14 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520849014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.1520849014
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.2540997402
Short name T41
Test name
Test status
Simulation time 33382757 ps
CPU time 1.35 seconds
Started Feb 09 02:03:46 PM UTC 25
Finished Feb 09 02:03:48 PM UTC 25
Peak memory 211136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540997402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2540997402
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.661045559
Short name T167
Test name
Test status
Simulation time 126257385 ps
CPU time 0.75 seconds
Started Feb 09 02:03:48 PM UTC 25
Finished Feb 09 02:03:50 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661045559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.661045559
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.2206956952
Short name T165
Test name
Test status
Simulation time 30811460 ps
CPU time 0.91 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:49 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206956952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.2206956952
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.1702639889
Short name T158
Test name
Test status
Simulation time 749901906 ps
CPU time 1.66 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:50 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702639889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1702639889
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.1767425806
Short name T18
Test name
Test status
Simulation time 57293590 ps
CPU time 0.96 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:49 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767425806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1767425806
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.1315416534
Short name T195
Test name
Test status
Simulation time 90906653 ps
CPU time 0.79 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:49 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315416534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1315416534
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.1861561363
Short name T45
Test name
Test status
Simulation time 47872648 ps
CPU time 1.14 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:03:51 PM UTC 25
Peak memory 210804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861561363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.1861561363
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.2030353262
Short name T81
Test name
Test status
Simulation time 201861729 ps
CPU time 1.15 seconds
Started Feb 09 02:03:45 PM UTC 25
Finished Feb 09 02:03:48 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030353262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.2030353262
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.2145193326
Short name T140
Test name
Test status
Simulation time 393907625 ps
CPU time 1.26 seconds
Started Feb 09 02:03:45 PM UTC 25
Finished Feb 09 02:03:48 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145193326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2145193326
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.285729068
Short name T43
Test name
Test status
Simulation time 93121915 ps
CPU time 1.26 seconds
Started Feb 09 02:03:48 PM UTC 25
Finished Feb 09 02:03:50 PM UTC 25
Peak memory 220144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285729068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.285729068
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.800694571
Short name T23
Test name
Test status
Simulation time 1614924679 ps
CPU time 1.83 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:03:52 PM UTC 25
Peak memory 236660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800694571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.800694571
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.972119048
Short name T173
Test name
Test status
Simulation time 875904050 ps
CPU time 3.3 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:51 PM UTC 25
Peak memory 211508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972119048 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.972119048
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.203112191
Short name T64
Test name
Test status
Simulation time 1052808608 ps
CPU time 2.77 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:51 PM UTC 25
Peak memory 210984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203112191 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.203112191
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3717072240
Short name T141
Test name
Test status
Simulation time 72594085 ps
CPU time 1.03 seconds
Started Feb 09 02:03:47 PM UTC 25
Finished Feb 09 02:03:49 PM UTC 25
Peak memory 208292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717072240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3717072240
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.2075951473
Short name T80
Test name
Test status
Simulation time 60991991 ps
CPU time 0.97 seconds
Started Feb 09 02:03:44 PM UTC 25
Finished Feb 09 02:03:46 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075951473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.2075951473
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.2215377566
Short name T185
Test name
Test status
Simulation time 298615096 ps
CPU time 1.74 seconds
Started Feb 09 02:03:45 PM UTC 25
Finished Feb 09 02:03:48 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215377566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.2215377566
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.2239509069
Short name T82
Test name
Test status
Simulation time 474526222 ps
CPU time 1.76 seconds
Started Feb 09 02:03:45 PM UTC 25
Finished Feb 09 02:03:49 PM UTC 25
Peak memory 210772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239509069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.2239509069
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.626852016
Short name T457
Test name
Test status
Simulation time 90135872 ps
CPU time 0.84 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626852016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.626852016
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.484688945
Short name T472
Test name
Test status
Simulation time 81976308 ps
CPU time 0.76 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:27 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484688945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.484688945
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2550095050
Short name T458
Test name
Test status
Simulation time 76687244 ps
CPU time 0.71 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550095050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.2550095050
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.2754291512
Short name T469
Test name
Test status
Simulation time 166292367 ps
CPU time 1.01 seconds
Started Feb 09 02:05:20 PM UTC 25
Finished Feb 09 02:05:22 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754291512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2754291512
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.961536785
Short name T451
Test name
Test status
Simulation time 65166375 ps
CPU time 0.86 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:27 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961536785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.961536785
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.2264480921
Short name T467
Test name
Test status
Simulation time 32772017 ps
CPU time 0.84 seconds
Started Feb 09 02:05:20 PM UTC 25
Finished Feb 09 02:05:22 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264480921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2264480921
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.3972026753
Short name T474
Test name
Test status
Simulation time 106184698 ps
CPU time 0.77 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:27 PM UTC 25
Peak memory 210472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972026753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.3972026753
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.1951218323
Short name T459
Test name
Test status
Simulation time 161404460 ps
CPU time 0.96 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951218323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.1951218323
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.2937915623
Short name T454
Test name
Test status
Simulation time 57479286 ps
CPU time 0.78 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937915623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.2937915623
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3354292595
Short name T477
Test name
Test status
Simulation time 104716436 ps
CPU time 1.02 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:27 PM UTC 25
Peak memory 210472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354292595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3354292595
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.2791085843
Short name T468
Test name
Test status
Simulation time 135635318 ps
CPU time 0.94 seconds
Started Feb 09 02:05:20 PM UTC 25
Finished Feb 09 02:05:22 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791085843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.2791085843
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3140664716
Short name T470
Test name
Test status
Simulation time 1008429708 ps
CPU time 2.75 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:22 PM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140664716 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3140664716
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2659599177
Short name T466
Test name
Test status
Simulation time 1155609359 ps
CPU time 2.07 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:21 PM UTC 25
Peak memory 211732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659599177 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2659599177
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.717280375
Short name T464
Test name
Test status
Simulation time 149179982 ps
CPU time 0.86 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717280375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.717280375
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.454556636
Short name T427
Test name
Test status
Simulation time 33421935 ps
CPU time 0.96 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:20 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454556636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.454556636
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.3170503874
Short name T495
Test name
Test status
Simulation time 1294743096 ps
CPU time 2.09 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 211452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170503874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3170503874
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.3979999784
Short name T534
Test name
Test status
Simulation time 11734682449 ps
CPU time 18.69 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:45 PM UTC 25
Peak memory 211020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3979999784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand
_reset.3979999784
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.457443410
Short name T449
Test name
Test status
Simulation time 221712715 ps
CPU time 1.28 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:21 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457443410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.457443410
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.3612854954
Short name T465
Test name
Test status
Simulation time 308373307 ps
CPU time 1.41 seconds
Started Feb 09 02:05:18 PM UTC 25
Finished Feb 09 02:05:21 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612854954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.3612854954
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.1151836412
Short name T478
Test name
Test status
Simulation time 59502441 ps
CPU time 0.81 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:27 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151836412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1151836412
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.3315438737
Short name T492
Test name
Test status
Simulation time 69067274 ps
CPU time 0.92 seconds
Started Feb 09 02:05:26 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 210868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315438737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.3315438737
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3443133568
Short name T490
Test name
Test status
Simulation time 29387330 ps
CPU time 0.94 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 208228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443133568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.3443133568
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.1790686983
Short name T491
Test name
Test status
Simulation time 162295803 ps
CPU time 1.06 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790686983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1790686983
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.4159249945
Short name T486
Test name
Test status
Simulation time 73496391 ps
CPU time 0.8 seconds
Started Feb 09 02:05:26 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159249945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.4159249945
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.1366625386
Short name T480
Test name
Test status
Simulation time 68942410 ps
CPU time 0.76 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366625386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1366625386
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.1811622122
Short name T489
Test name
Test status
Simulation time 43855500 ps
CPU time 0.75 seconds
Started Feb 09 02:05:26 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 209224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811622122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.1811622122
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.2968732391
Short name T484
Test name
Test status
Simulation time 208812453 ps
CPU time 1.12 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968732391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.2968732391
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.578389260
Short name T485
Test name
Test status
Simulation time 38268630 ps
CPU time 1.1 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578389260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.578389260
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.3613446045
Short name T493
Test name
Test status
Simulation time 500003104 ps
CPU time 1.02 seconds
Started Feb 09 02:05:26 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613446045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3613446045
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.145882237
Short name T494
Test name
Test status
Simulation time 263456538 ps
CPU time 1.46 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 211088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145882237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.145882237
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.426570330
Short name T496
Test name
Test status
Simulation time 909478739 ps
CPU time 1.98 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:29 PM UTC 25
Peak memory 211372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426570330 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.426570330
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.571305605
Short name T497
Test name
Test status
Simulation time 1316622373 ps
CPU time 2.66 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:29 PM UTC 25
Peak memory 211284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571305605 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.571305605
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3729906214
Short name T482
Test name
Test status
Simulation time 50933686 ps
CPU time 0.94 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729906214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3729906214
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.3311418878
Short name T476
Test name
Test status
Simulation time 32425982 ps
CPU time 0.83 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:27 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311418878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3311418878
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.3971308712
Short name T518
Test name
Test status
Simulation time 2339723135 ps
CPU time 2.19 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 211600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971308712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.3971308712
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.3845601039
Short name T552
Test name
Test status
Simulation time 6067622664 ps
CPU time 14.51 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:48 PM UTC 25
Peak memory 211628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3845601039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand
_reset.3845601039
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.632727348
Short name T488
Test name
Test status
Simulation time 277140674 ps
CPU time 1.2 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632727348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.632727348
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.2452449675
Short name T487
Test name
Test status
Simulation time 318367021 ps
CPU time 1.22 seconds
Started Feb 09 02:05:25 PM UTC 25
Finished Feb 09 02:05:28 PM UTC 25
Peak memory 210656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452449675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.2452449675
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.4073210254
Short name T503
Test name
Test status
Simulation time 34270966 ps
CPU time 0.83 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073210254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.4073210254
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3637374964
Short name T515
Test name
Test status
Simulation time 43040979 ps
CPU time 0.95 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 210440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637374964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.3637374964
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.4114695657
Short name T508
Test name
Test status
Simulation time 30252995 ps
CPU time 0.85 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114695657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.4114695657
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.2181181599
Short name T517
Test name
Test status
Simulation time 161306777 ps
CPU time 1.37 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 206272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181181599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2181181599
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.736559931
Short name T507
Test name
Test status
Simulation time 38945850 ps
CPU time 0.71 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736559931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.736559931
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.210664240
Short name T505
Test name
Test status
Simulation time 140564963 ps
CPU time 0.82 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 206420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210664240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.210664240
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.4118148037
Short name T514
Test name
Test status
Simulation time 101536805 ps
CPU time 0.88 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118148037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.4118148037
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.1602478317
Short name T511
Test name
Test status
Simulation time 307911672 ps
CPU time 1.28 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602478317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.1602478317
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.4002006799
Short name T500
Test name
Test status
Simulation time 43993232 ps
CPU time 0.67 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002006799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.4002006799
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.1765956411
Short name T519
Test name
Test status
Simulation time 110971382 ps
CPU time 1.52 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765956411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1765956411
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.19653641
Short name T512
Test name
Test status
Simulation time 76965587 ps
CPU time 1.04 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19653641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.19653641
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1863198819
Short name T520
Test name
Test status
Simulation time 1104823797 ps
CPU time 2.46 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:36 PM UTC 25
Peak memory 211400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863198819 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1863198819
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3296345814
Short name T521
Test name
Test status
Simulation time 1274280914 ps
CPU time 2.37 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:36 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296345814 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3296345814
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3146786393
Short name T510
Test name
Test status
Simulation time 105830156 ps
CPU time 1.03 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146786393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3146786393
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.376973045
Short name T504
Test name
Test status
Simulation time 47023354 ps
CPU time 0.89 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376973045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.376973045
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.1662898521
Short name T523
Test name
Test status
Simulation time 2059571711 ps
CPU time 4.01 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:38 PM UTC 25
Peak memory 211044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662898521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.1662898521
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.2178158913
Short name T85
Test name
Test status
Simulation time 14014920298 ps
CPU time 19.46 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:53 PM UTC 25
Peak memory 211216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2178158913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand
_reset.2178158913
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.3330422383
Short name T501
Test name
Test status
Simulation time 56994582 ps
CPU time 0.74 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330422383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.3330422383
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.3813353296
Short name T509
Test name
Test status
Simulation time 111604604 ps
CPU time 1.24 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:34 PM UTC 25
Peak memory 210836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813353296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.3813353296
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.4270764806
Short name T525
Test name
Test status
Simulation time 36057856 ps
CPU time 0.89 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270764806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.4270764806
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3777616749
Short name T502
Test name
Test status
Simulation time 85587601 ps
CPU time 0.85 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 210828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777616749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.3777616749
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3019037778
Short name T473
Test name
Test status
Simulation time 30105431 ps
CPU time 0.92 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019037778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.3019037778
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.217983709
Short name T530
Test name
Test status
Simulation time 167874822 ps
CPU time 1.07 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:40 PM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217983709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.217983709
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.2193037688
Short name T475
Test name
Test status
Simulation time 71960183 ps
CPU time 0.78 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193037688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2193037688
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.2505073584
Short name T483
Test name
Test status
Simulation time 22715511 ps
CPU time 0.79 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505073584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.2505073584
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.3383561324
Short name T479
Test name
Test status
Simulation time 43887253 ps
CPU time 0.83 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:40 PM UTC 25
Peak memory 210432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383561324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.3383561324
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2646362059
Short name T506
Test name
Test status
Simulation time 247996813 ps
CPU time 1.46 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646362059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.2646362059
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.4232351401
Short name T516
Test name
Test status
Simulation time 66940138 ps
CPU time 0.99 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232351401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.4232351401
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.234619306
Short name T481
Test name
Test status
Simulation time 145510411 ps
CPU time 1 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:40 PM UTC 25
Peak memory 220140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234619306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.234619306
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2349397844
Short name T531
Test name
Test status
Simulation time 159999407 ps
CPU time 1.24 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349397844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.2349397844
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.513836496
Short name T532
Test name
Test status
Simulation time 1230211096 ps
CPU time 1.97 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:40 PM UTC 25
Peak memory 210652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513836496 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.513836496
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3769716848
Short name T533
Test name
Test status
Simulation time 1627102881 ps
CPU time 2.49 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:41 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769716848 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3769716848
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1833068456
Short name T529
Test name
Test status
Simulation time 122382798 ps
CPU time 0.93 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833068456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1833068456
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.2395541292
Short name T513
Test name
Test status
Simulation time 36014877 ps
CPU time 0.73 seconds
Started Feb 09 02:05:32 PM UTC 25
Finished Feb 09 02:05:35 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395541292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2395541292
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.3469861055
Short name T548
Test name
Test status
Simulation time 745940441 ps
CPU time 1.75 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 210792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469861055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.3469861055
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.547221018
Short name T96
Test name
Test status
Simulation time 9730448412 ps
CPU time 13.27 seconds
Started Feb 09 02:05:38 PM UTC 25
Finished Feb 09 02:05:52 PM UTC 25
Peak memory 211880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=547221018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_
reset.547221018
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.3197876362
Short name T528
Test name
Test status
Simulation time 257644591 ps
CPU time 1.02 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197876362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.3197876362
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.2929607939
Short name T527
Test name
Test status
Simulation time 210229378 ps
CPU time 0.95 seconds
Started Feb 09 02:05:37 PM UTC 25
Finished Feb 09 02:05:39 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929607939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.2929607939
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3469635168
Short name T538
Test name
Test status
Simulation time 36768137 ps
CPU time 1.15 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469635168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3469635168
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.3947956394
Short name T542
Test name
Test status
Simulation time 64394834 ps
CPU time 0.93 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947956394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.3947956394
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2439973804
Short name T536
Test name
Test status
Simulation time 31971932 ps
CPU time 0.74 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439973804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.2439973804
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.1032544251
Short name T544
Test name
Test status
Simulation time 835944541 ps
CPU time 1.07 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032544251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.1032544251
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.507710192
Short name T541
Test name
Test status
Simulation time 53865378 ps
CPU time 0.87 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507710192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.507710192
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.170141866
Short name T537
Test name
Test status
Simulation time 144771841 ps
CPU time 0.75 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170141866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.170141866
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.2183689544
Short name T543
Test name
Test status
Simulation time 55038024 ps
CPU time 0.89 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 210960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183689544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.2183689544
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.3642124105
Short name T535
Test name
Test status
Simulation time 206971290 ps
CPU time 0.99 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642124105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.3642124105
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.3569324191
Short name T526
Test name
Test status
Simulation time 28039365 ps
CPU time 0.8 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569324191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3569324191
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.576659696
Short name T549
Test name
Test status
Simulation time 115191109 ps
CPU time 1.14 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576659696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.576659696
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1549626634
Short name T550
Test name
Test status
Simulation time 286989042 ps
CPU time 1.52 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549626634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.1549626634
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3608764599
Short name T553
Test name
Test status
Simulation time 784193782 ps
CPU time 3.16 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:48 PM UTC 25
Peak memory 211360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608764599 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3608764599
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3786450386
Short name T551
Test name
Test status
Simulation time 1109441122 ps
CPU time 2.04 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 211744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786450386 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3786450386
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.446856235
Short name T540
Test name
Test status
Simulation time 109321021 ps
CPU time 1.08 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446856235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.446856235
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2018636361
Short name T499
Test name
Test status
Simulation time 67561302 ps
CPU time 0.68 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018636361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2018636361
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.1264378731
Short name T554
Test name
Test status
Simulation time 3891656168 ps
CPU time 3.15 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:49 PM UTC 25
Peak memory 211484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264378731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.1264378731
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.3192444000
Short name T572
Test name
Test status
Simulation time 7832176753 ps
CPU time 9.65 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:55 PM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3192444000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand
_reset.3192444000
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.4020161662
Short name T524
Test name
Test status
Simulation time 174611863 ps
CPU time 0.79 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020161662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.4020161662
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.3129207362
Short name T539
Test name
Test status
Simulation time 102539393 ps
CPU time 1.16 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:46 PM UTC 25
Peak memory 211016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129207362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.3129207362
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.341406494
Short name T561
Test name
Test status
Simulation time 119315831 ps
CPU time 1.07 seconds
Started Feb 09 02:05:51 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 211016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341406494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.341406494
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.953714505
Short name T190
Test name
Test status
Simulation time 60846204 ps
CPU time 0.94 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953714505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.953714505
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1480412600
Short name T556
Test name
Test status
Simulation time 32852280 ps
CPU time 0.76 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480412600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.1480412600
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.2178527639
Short name T568
Test name
Test status
Simulation time 168730667 ps
CPU time 1.28 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178527639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2178527639
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.1243124837
Short name T555
Test name
Test status
Simulation time 61163325 ps
CPU time 0.73 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243124837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1243124837
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.1228488885
Short name T558
Test name
Test status
Simulation time 69202756 ps
CPU time 0.8 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228488885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.1228488885
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.369865100
Short name T564
Test name
Test status
Simulation time 76181102 ps
CPU time 0.86 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369865100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.369865100
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.900985548
Short name T545
Test name
Test status
Simulation time 104265839 ps
CPU time 0.82 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900985548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.900985548
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.350262488
Short name T547
Test name
Test status
Simulation time 44203276 ps
CPU time 0.92 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350262488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.350262488
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.4276627579
Short name T569
Test name
Test status
Simulation time 101163609 ps
CPU time 1.36 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276627579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.4276627579
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.2933040874
Short name T562
Test name
Test status
Simulation time 131594088 ps
CPU time 0.83 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933040874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.2933040874
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3852457153
Short name T571
Test name
Test status
Simulation time 810047835 ps
CPU time 2.43 seconds
Started Feb 09 02:05:51 PM UTC 25
Finished Feb 09 02:05:55 PM UTC 25
Peak memory 211524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852457153 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3852457153
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3613499816
Short name T573
Test name
Test status
Simulation time 978045259 ps
CPU time 3.42 seconds
Started Feb 09 02:05:51 PM UTC 25
Finished Feb 09 02:05:56 PM UTC 25
Peak memory 211312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613499816 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3613499816
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.445952683
Short name T560
Test name
Test status
Simulation time 92578233 ps
CPU time 0.9 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445952683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.445952683
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.2121628567
Short name T546
Test name
Test status
Simulation time 26280432 ps
CPU time 0.91 seconds
Started Feb 09 02:05:44 PM UTC 25
Finished Feb 09 02:05:47 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121628567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2121628567
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.1054467572
Short name T574
Test name
Test status
Simulation time 724595234 ps
CPU time 3.51 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:57 PM UTC 25
Peak memory 211532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054467572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1054467572
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.2601626540
Short name T575
Test name
Test status
Simulation time 4534046195 ps
CPU time 6.72 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:06:00 PM UTC 25
Peak memory 211936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2601626540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand
_reset.2601626540
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.3855259938
Short name T559
Test name
Test status
Simulation time 124612572 ps
CPU time 1.02 seconds
Started Feb 09 02:05:51 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855259938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.3855259938
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.3864845872
Short name T557
Test name
Test status
Simulation time 52975222 ps
CPU time 0.97 seconds
Started Feb 09 02:05:51 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 210668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864845872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.3864845872
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.260094198
Short name T578
Test name
Test status
Simulation time 33523798 ps
CPU time 0.88 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 210928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260094198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.260094198
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.382090624
Short name T582
Test name
Test status
Simulation time 63873595 ps
CPU time 0.88 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 210840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382090624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.382090624
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.915700908
Short name T577
Test name
Test status
Simulation time 29829467 ps
CPU time 0.76 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915700908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.915700908
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.64211863
Short name T587
Test name
Test status
Simulation time 891049198 ps
CPU time 1.17 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:02 PM UTC 25
Peak memory 208760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64211863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esca
lation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.64211863
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.2950678079
Short name T581
Test name
Test status
Simulation time 75438463 ps
CPU time 0.83 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 208308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950678079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2950678079
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2274859515
Short name T580
Test name
Test status
Simulation time 65060458 ps
CPU time 0.86 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274859515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2274859515
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.56624303
Short name T585
Test name
Test status
Simulation time 56935490 ps
CPU time 0.85 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56624303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.56624303
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.3772163245
Short name T566
Test name
Test status
Simulation time 88967249 ps
CPU time 0.79 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772163245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.3772163245
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.978464917
Short name T565
Test name
Test status
Simulation time 52278829 ps
CPU time 0.72 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978464917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.978464917
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.2437566103
Short name T590
Test name
Test status
Simulation time 98324262 ps
CPU time 1.41 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:02 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437566103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.2437566103
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.250428732
Short name T576
Test name
Test status
Simulation time 59200116 ps
CPU time 0.69 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250428732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.250428732
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2762911107
Short name T593
Test name
Test status
Simulation time 889726671 ps
CPU time 3.31 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:03 PM UTC 25
Peak memory 211368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762911107 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2762911107
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.141877348
Short name T592
Test name
Test status
Simulation time 896056626 ps
CPU time 2.79 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:03 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141877348 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.141877348
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2959107895
Short name T579
Test name
Test status
Simulation time 50282720 ps
CPU time 1.02 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959107895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2959107895
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.93956162
Short name T563
Test name
Test status
Simulation time 57434524 ps
CPU time 0.89 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93956162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.93956162
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.2889509996
Short name T594
Test name
Test status
Simulation time 2026448650 ps
CPU time 3.05 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:03 PM UTC 25
Peak memory 211520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889509996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.2889509996
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3515825810
Short name T656
Test name
Test status
Simulation time 7676472286 ps
CPU time 22.21 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:23 PM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3515825810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand
_reset.3515825810
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.2426979174
Short name T567
Test name
Test status
Simulation time 70701470 ps
CPU time 0.87 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:54 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426979174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2426979174
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.3193303550
Short name T570
Test name
Test status
Simulation time 272848221 ps
CPU time 1.53 seconds
Started Feb 09 02:05:52 PM UTC 25
Finished Feb 09 02:05:55 PM UTC 25
Peak memory 210896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193303550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.3193303550
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.1447292839
Short name T588
Test name
Test status
Simulation time 40766615 ps
CPU time 0.83 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:02 PM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447292839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1447292839
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.3313086265
Short name T597
Test name
Test status
Simulation time 37809376 ps
CPU time 0.63 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313086265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.3313086265
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.2905888346
Short name T604
Test name
Test status
Simulation time 164059687 ps
CPU time 1.02 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905888346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2905888346
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.1934619051
Short name T599
Test name
Test status
Simulation time 22849922 ps
CPU time 0.64 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934619051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.1934619051
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.3088212778
Short name T600
Test name
Test status
Simulation time 33871763 ps
CPU time 0.73 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088212778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3088212778
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.2624157735
Short name T603
Test name
Test status
Simulation time 71562594 ps
CPU time 0.75 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 210436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624157735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.2624157735
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.498671208
Short name T584
Test name
Test status
Simulation time 209480641 ps
CPU time 0.74 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498671208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.498671208
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.723214883
Short name T586
Test name
Test status
Simulation time 38418745 ps
CPU time 0.88 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723214883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.723214883
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.1749838015
Short name T606
Test name
Test status
Simulation time 129454000 ps
CPU time 0.94 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 219644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749838015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1749838015
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1390175888
Short name T602
Test name
Test status
Simulation time 292508740 ps
CPU time 0.95 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390175888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.1390175888
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1143718826
Short name T595
Test name
Test status
Simulation time 830412480 ps
CPU time 3.21 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:04 PM UTC 25
Peak memory 211432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143718826 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1143718826
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2417867315
Short name T596
Test name
Test status
Simulation time 899542681 ps
CPU time 3.49 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:04 PM UTC 25
Peak memory 211588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417867315 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2417867315
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3005365869
Short name T598
Test name
Test status
Simulation time 77091804 ps
CPU time 0.82 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:09 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005365869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3005365869
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.2061457919
Short name T583
Test name
Test status
Simulation time 43794912 ps
CPU time 0.7 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:01 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061457919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2061457919
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.2101124037
Short name T624
Test name
Test status
Simulation time 2109950942 ps
CPU time 3.7 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:12 PM UTC 25
Peak memory 211388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101124037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.2101124037
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.2940300133
Short name T625
Test name
Test status
Simulation time 9551584723 ps
CPU time 6.67 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:15 PM UTC 25
Peak memory 211840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2940300133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand
_reset.2940300133
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.2928617718
Short name T589
Test name
Test status
Simulation time 441252276 ps
CPU time 1.07 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:02 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928617718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2928617718
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.3680604016
Short name T591
Test name
Test status
Simulation time 373471501 ps
CPU time 1.2 seconds
Started Feb 09 02:05:59 PM UTC 25
Finished Feb 09 02:06:02 PM UTC 25
Peak memory 210956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680604016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.3680604016
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.4156743930
Short name T611
Test name
Test status
Simulation time 89889055 ps
CPU time 0.87 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156743930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.4156743930
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.1046663613
Short name T622
Test name
Test status
Simulation time 67641010 ps
CPU time 0.84 seconds
Started Feb 09 02:06:10 PM UTC 25
Finished Feb 09 02:06:12 PM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046663613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.1046663613
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2543475865
Short name T612
Test name
Test status
Simulation time 33423198 ps
CPU time 0.63 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543475865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.2543475865
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.557530108
Short name T617
Test name
Test status
Simulation time 319745525 ps
CPU time 1.12 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557530108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.557530108
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.2317674328
Short name T620
Test name
Test status
Simulation time 62063124 ps
CPU time 0.69 seconds
Started Feb 09 02:06:10 PM UTC 25
Finished Feb 09 02:06:12 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317674328 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.2317674328
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.2280358828
Short name T613
Test name
Test status
Simulation time 80505175 ps
CPU time 0.79 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280358828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2280358828
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.929851794
Short name T628
Test name
Test status
Simulation time 50806478 ps
CPU time 0.78 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929851794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.929851794
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.3133711885
Short name T608
Test name
Test status
Simulation time 67245265 ps
CPU time 0.83 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133711885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.3133711885
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.547736353
Short name T609
Test name
Test status
Simulation time 124494562 ps
CPU time 0.9 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 210848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547736353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.547736353
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.1035039415
Short name T621
Test name
Test status
Simulation time 162080898 ps
CPU time 0.74 seconds
Started Feb 09 02:06:10 PM UTC 25
Finished Feb 09 02:06:12 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035039415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1035039415
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.3063793286
Short name T618
Test name
Test status
Simulation time 321282168 ps
CPU time 1.59 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:11 PM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063793286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.3063793286
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4162838085
Short name T619
Test name
Test status
Simulation time 1090089055 ps
CPU time 2.2 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:11 PM UTC 25
Peak memory 211216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162838085 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4162838085
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1804520263
Short name T623
Test name
Test status
Simulation time 848755766 ps
CPU time 3.06 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:12 PM UTC 25
Peak memory 211240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804520263 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1804520263
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3251268419
Short name T615
Test name
Test status
Simulation time 95915496 ps
CPU time 0.9 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251268419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.3251268419
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.2214324237
Short name T605
Test name
Test status
Simulation time 31420828 ps
CPU time 0.74 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214324237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2214324237
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.2258634016
Short name T631
Test name
Test status
Simulation time 325199108 ps
CPU time 0.98 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258634016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.2258634016
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.3818534179
Short name T97
Test name
Test status
Simulation time 17127304136 ps
CPU time 15.81 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:35 PM UTC 25
Peak memory 211704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3818534179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand
_reset.3818534179
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.635796007
Short name T614
Test name
Test status
Simulation time 130925777 ps
CPU time 0.99 seconds
Started Feb 09 02:06:07 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635796007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.635796007
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.4033070365
Short name T616
Test name
Test status
Simulation time 153573786 ps
CPU time 1.15 seconds
Started Feb 09 02:06:08 PM UTC 25
Finished Feb 09 02:06:10 PM UTC 25
Peak memory 210896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033070365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.4033070365
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.3009292778
Short name T638
Test name
Test status
Simulation time 29527882 ps
CPU time 1.01 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 211164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009292778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3009292778
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.650117389
Short name T643
Test name
Test status
Simulation time 54413758 ps
CPU time 0.89 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650117389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.650117389
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3846226494
Short name T635
Test name
Test status
Simulation time 37800206 ps
CPU time 0.74 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846226494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.3846226494
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.3918303465
Short name T647
Test name
Test status
Simulation time 629491640 ps
CPU time 1.27 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918303465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3918303465
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.3362036460
Short name T636
Test name
Test status
Simulation time 35834953 ps
CPU time 0.7 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362036460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.3362036460
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.2908118988
Short name T639
Test name
Test status
Simulation time 30035664 ps
CPU time 0.75 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908118988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2908118988
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.810686610
Short name T641
Test name
Test status
Simulation time 75933470 ps
CPU time 0.8 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810686610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.810686610
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.3746103683
Short name T630
Test name
Test status
Simulation time 193653474 ps
CPU time 0.88 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746103683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.3746103683
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.684682293
Short name T637
Test name
Test status
Simulation time 175034746 ps
CPU time 1.12 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684682293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.684682293
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.3567715632
Short name T642
Test name
Test status
Simulation time 150123317 ps
CPU time 0.87 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567715632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3567715632
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2361362857
Short name T648
Test name
Test status
Simulation time 162905904 ps
CPU time 1.37 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361362857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.2361362857
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4122692029
Short name T654
Test name
Test status
Simulation time 993014168 ps
CPU time 2.4 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:22 PM UTC 25
Peak memory 211632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122692029 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4122692029
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.778712344
Short name T655
Test name
Test status
Simulation time 931971213 ps
CPU time 2.4 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:22 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778712344 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.778712344
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3591211766
Short name T640
Test name
Test status
Simulation time 407498041 ps
CPU time 0.96 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591211766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3591211766
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.2891999906
Short name T626
Test name
Test status
Simulation time 61667326 ps
CPU time 0.75 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891999906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2891999906
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.3513326206
Short name T652
Test name
Test status
Simulation time 529102596 ps
CPU time 1.74 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 210852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513326206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.3513326206
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.1681154576
Short name T74
Test name
Test status
Simulation time 10974053541 ps
CPU time 40.35 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:07:00 PM UTC 25
Peak memory 221084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1681154576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand
_reset.1681154576
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.4161451078
Short name T627
Test name
Test status
Simulation time 90667846 ps
CPU time 0.7 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:20 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161451078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.4161451078
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.3868860368
Short name T649
Test name
Test status
Simulation time 376289390 ps
CPU time 1.7 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 211180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868860368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.3868860368
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.2377861012
Short name T169
Test name
Test status
Simulation time 61144138 ps
CPU time 1.11 seconds
Started Feb 09 02:03:53 PM UTC 25
Finished Feb 09 02:03:56 PM UTC 25
Peak memory 210716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377861012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.2377861012
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.4226502078
Short name T166
Test name
Test status
Simulation time 28533832 ps
CPU time 0.95 seconds
Started Feb 09 02:03:52 PM UTC 25
Finished Feb 09 02:03:54 PM UTC 25
Peak memory 206360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226502078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.4226502078
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3515272582
Short name T159
Test name
Test status
Simulation time 185385149 ps
CPU time 1.36 seconds
Started Feb 09 02:03:52 PM UTC 25
Finished Feb 09 02:03:55 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515272582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3515272582
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.3488547498
Short name T19
Test name
Test status
Simulation time 35574682 ps
CPU time 0.88 seconds
Started Feb 09 02:03:52 PM UTC 25
Finished Feb 09 02:03:54 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488547498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.3488547498
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.3837801029
Short name T197
Test name
Test status
Simulation time 48950372 ps
CPU time 0.95 seconds
Started Feb 09 02:03:52 PM UTC 25
Finished Feb 09 02:03:54 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837801029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.3837801029
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.3142376640
Short name T204
Test name
Test status
Simulation time 47973014 ps
CPU time 0.95 seconds
Started Feb 09 02:03:53 PM UTC 25
Finished Feb 09 02:03:56 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142376640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.3142376640
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.914469203
Short name T83
Test name
Test status
Simulation time 124620069 ps
CPU time 1.24 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:03:52 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914469203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.914469203
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2987632851
Short name T198
Test name
Test status
Simulation time 67988369 ps
CPU time 1.21 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:03:52 PM UTC 25
Peak memory 208428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987632851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2987632851
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.579526664
Short name T203
Test name
Test status
Simulation time 147421529 ps
CPU time 0.97 seconds
Started Feb 09 02:03:53 PM UTC 25
Finished Feb 09 02:03:56 PM UTC 25
Peak memory 220144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579526664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.579526664
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.2059071772
Short name T30
Test name
Test status
Simulation time 1097282156 ps
CPU time 1.54 seconds
Started Feb 09 02:03:53 PM UTC 25
Finished Feb 09 02:03:56 PM UTC 25
Peak memory 236872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059071772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2059071772
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1747254735
Short name T202
Test name
Test status
Simulation time 170520640 ps
CPU time 1.42 seconds
Started Feb 09 02:03:52 PM UTC 25
Finished Feb 09 02:03:55 PM UTC 25
Peak memory 208344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747254735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.1747254735
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2947552864
Short name T174
Test name
Test status
Simulation time 747700327 ps
CPU time 2.96 seconds
Started Feb 09 02:03:51 PM UTC 25
Finished Feb 09 02:03:55 PM UTC 25
Peak memory 211408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947552864 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2947552864
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1440856491
Short name T168
Test name
Test status
Simulation time 1507897970 ps
CPU time 2.28 seconds
Started Feb 09 02:03:51 PM UTC 25
Finished Feb 09 02:03:54 PM UTC 25
Peak memory 211304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440856491 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1440856491
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1894003383
Short name T200
Test name
Test status
Simulation time 152890121 ps
CPU time 1.1 seconds
Started Feb 09 02:03:51 PM UTC 25
Finished Feb 09 02:03:53 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894003383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.1894003383
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2728378119
Short name T196
Test name
Test status
Simulation time 27669750 ps
CPU time 1 seconds
Started Feb 09 02:03:49 PM UTC 25
Finished Feb 09 02:03:52 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728378119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2728378119
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.3142261048
Short name T108
Test name
Test status
Simulation time 2120275685 ps
CPU time 4.9 seconds
Started Feb 09 02:03:53 PM UTC 25
Finished Feb 09 02:04:00 PM UTC 25
Peak memory 211408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142261048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.3142261048
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.4289801733
Short name T89
Test name
Test status
Simulation time 10680097966 ps
CPU time 22.31 seconds
Started Feb 09 02:03:53 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4289801733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_
reset.4289801733
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.2184924051
Short name T199
Test name
Test status
Simulation time 210535906 ps
CPU time 1.19 seconds
Started Feb 09 02:03:50 PM UTC 25
Finished Feb 09 02:03:52 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184924051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2184924051
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.251405389
Short name T201
Test name
Test status
Simulation time 164582505 ps
CPU time 1.82 seconds
Started Feb 09 02:03:51 PM UTC 25
Finished Feb 09 02:03:54 PM UTC 25
Peak memory 210696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251405389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.251405389
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.2800525185
Short name T653
Test name
Test status
Simulation time 41825475 ps
CPU time 0.71 seconds
Started Feb 09 02:06:20 PM UTC 25
Finished Feb 09 02:06:22 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800525185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.2800525185
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1209915770
Short name T662
Test name
Test status
Simulation time 30152644 ps
CPU time 0.79 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209915770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.1209915770
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.166626715
Short name T633
Test name
Test status
Simulation time 162562622 ps
CPU time 1.12 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166626715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.166626715
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.3116569996
Short name T661
Test name
Test status
Simulation time 54862392 ps
CPU time 0.66 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 206468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116569996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3116569996
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.2896925268
Short name T659
Test name
Test status
Simulation time 48655741 ps
CPU time 0.6 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896925268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.2896925268
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.3480804229
Short name T663
Test name
Test status
Simulation time 86830260 ps
CPU time 0.73 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480804229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.3480804229
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.1336455486
Short name T645
Test name
Test status
Simulation time 230165114 ps
CPU time 0.83 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336455486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.1336455486
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.235916861
Short name T646
Test name
Test status
Simulation time 29464427 ps
CPU time 0.84 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235916861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.235916861
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.1672277000
Short name T632
Test name
Test status
Simulation time 151666623 ps
CPU time 0.93 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672277000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1672277000
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.452703135
Short name T664
Test name
Test status
Simulation time 348218997 ps
CPU time 0.94 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452703135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.452703135
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2968125002
Short name T669
Test name
Test status
Simulation time 2907377296 ps
CPU time 2.23 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 211696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968125002 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2968125002
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3364068443
Short name T671
Test name
Test status
Simulation time 1045834109 ps
CPU time 2.08 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 211268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364068443 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3364068443
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4125549146
Short name T660
Test name
Test status
Simulation time 67440956 ps
CPU time 0.96 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:30 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125549146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4125549146
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2112510777
Short name T644
Test name
Test status
Simulation time 31200275 ps
CPU time 0.83 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112510777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2112510777
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.303500423
Short name T668
Test name
Test status
Simulation time 449628096 ps
CPU time 1.27 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 211132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303500423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.303500423
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.991389235
Short name T676
Test name
Test status
Simulation time 4109002812 ps
CPU time 9.71 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:39 PM UTC 25
Peak memory 211556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=991389235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_
reset.991389235
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.2000788740
Short name T651
Test name
Test status
Simulation time 180953058 ps
CPU time 1.13 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000788740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.2000788740
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.4154431619
Short name T650
Test name
Test status
Simulation time 298604009 ps
CPU time 1.01 seconds
Started Feb 09 02:06:18 PM UTC 25
Finished Feb 09 02:06:21 PM UTC 25
Peak memory 211136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154431619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.4154431619
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3147286264
Short name T607
Test name
Test status
Simulation time 44865836 ps
CPU time 0.92 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147286264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3147286264
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.1523481736
Short name T673
Test name
Test status
Simulation time 69845128 ps
CPU time 0.9 seconds
Started Feb 09 02:06:30 PM UTC 25
Finished Feb 09 02:06:32 PM UTC 25
Peak memory 210840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523481736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.1523481736
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3306386802
Short name T666
Test name
Test status
Simulation time 33187024 ps
CPU time 0.62 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306386802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.3306386802
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.1467398156
Short name T670
Test name
Test status
Simulation time 311683086 ps
CPU time 1.17 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467398156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1467398156
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.1701804897
Short name T601
Test name
Test status
Simulation time 71504320 ps
CPU time 0.61 seconds
Started Feb 09 02:06:29 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701804897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1701804897
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.3081663023
Short name T610
Test name
Test status
Simulation time 46180739 ps
CPU time 0.72 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081663023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3081663023
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.1543784426
Short name T678
Test name
Test status
Simulation time 43032585 ps
CPU time 0.72 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543784426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.1543784426
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.2868778299
Short name T657
Test name
Test status
Simulation time 63122986 ps
CPU time 0.91 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868778299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.2868778299
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.3325534895
Short name T658
Test name
Test status
Simulation time 64496580 ps
CPU time 1.24 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325534895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3325534895
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3150879784
Short name T679
Test name
Test status
Simulation time 95906828 ps
CPU time 1.01 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150879784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3150879784
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1671646421
Short name T672
Test name
Test status
Simulation time 212500976 ps
CPU time 1.43 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671646421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.1671646421
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.536934431
Short name T674
Test name
Test status
Simulation time 764114552 ps
CPU time 2.56 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:32 PM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536934431 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.536934431
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2560651143
Short name T675
Test name
Test status
Simulation time 900405232 ps
CPU time 3.64 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:34 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560651143 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2560651143
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3218049111
Short name T667
Test name
Test status
Simulation time 53559161 ps
CPU time 1.04 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218049111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3218049111
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.1957476171
Short name T665
Test name
Test status
Simulation time 29034540 ps
CPU time 0.78 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957476171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1957476171
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.1271343855
Short name T697
Test name
Test status
Simulation time 1437035344 ps
CPU time 2.64 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:42 PM UTC 25
Peak memory 211420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271343855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.1271343855
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3863911834
Short name T700
Test name
Test status
Simulation time 9064885771 ps
CPU time 6.98 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:46 PM UTC 25
Peak memory 211884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3863911834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand
_reset.3863911834
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.2753246170
Short name T634
Test name
Test status
Simulation time 62705543 ps
CPU time 0.93 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753246170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2753246170
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.2735253114
Short name T629
Test name
Test status
Simulation time 174180564 ps
CPU time 1.01 seconds
Started Feb 09 02:06:28 PM UTC 25
Finished Feb 09 02:06:31 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735253114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.2735253114
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.460619247
Short name T681
Test name
Test status
Simulation time 27532718 ps
CPU time 0.8 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460619247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.460619247
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.2329354082
Short name T688
Test name
Test status
Simulation time 103899500 ps
CPU time 0.75 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 208524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329354082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.2329354082
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.3779416548
Short name T685
Test name
Test status
Simulation time 31321867 ps
CPU time 0.86 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 206060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779416548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.3779416548
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.2258764216
Short name T693
Test name
Test status
Simulation time 638403185 ps
CPU time 1.16 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258764216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2258764216
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.944285575
Short name T684
Test name
Test status
Simulation time 56057633 ps
CPU time 0.72 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944285575 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.944285575
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.1326195446
Short name T682
Test name
Test status
Simulation time 51900602 ps
CPU time 0.64 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326195446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1326195446
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.2476604510
Short name T686
Test name
Test status
Simulation time 110402701 ps
CPU time 0.7 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476604510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.2476604510
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.1919391498
Short name T691
Test name
Test status
Simulation time 268064365 ps
CPU time 1.43 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919391498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.1919391498
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.795929242
Short name T680
Test name
Test status
Simulation time 29360010 ps
CPU time 0.77 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795929242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.795929242
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.1951542968
Short name T687
Test name
Test status
Simulation time 286420686 ps
CPU time 0.77 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951542968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1951542968
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.2470975033
Short name T695
Test name
Test status
Simulation time 224007306 ps
CPU time 1.4 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470975033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.2470975033
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3163694557
Short name T698
Test name
Test status
Simulation time 961312630 ps
CPU time 2.78 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:42 PM UTC 25
Peak memory 211640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163694557 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3163694557
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4007460130
Short name T699
Test name
Test status
Simulation time 913234955 ps
CPU time 3.04 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:43 PM UTC 25
Peak memory 211348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007460130 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4007460130
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2617096464
Short name T692
Test name
Test status
Simulation time 69394781 ps
CPU time 1.27 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 207968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617096464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2617096464
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.439879165
Short name T677
Test name
Test status
Simulation time 69322443 ps
CPU time 0.64 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439879165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.439879165
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.3615993398
Short name T696
Test name
Test status
Simulation time 256149270 ps
CPU time 1.42 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:42 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615993398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3615993398
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.365615281
Short name T771
Test name
Test status
Simulation time 8098998065 ps
CPU time 27.34 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:07:07 PM UTC 25
Peak memory 211608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=365615281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_
reset.365615281
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.272025952
Short name T683
Test name
Test status
Simulation time 121439082 ps
CPU time 1.05 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:40 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272025952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.272025952
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.295359321
Short name T694
Test name
Test status
Simulation time 224241521 ps
CPU time 1.54 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 210712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295359321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.295359321
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.2487272250
Short name T708
Test name
Test status
Simulation time 62115187 ps
CPU time 1.08 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 211140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487272250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.2487272250
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2530693159
Short name T704
Test name
Test status
Simulation time 70971336 ps
CPU time 0.74 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530693159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.2530693159
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2151235801
Short name T703
Test name
Test status
Simulation time 32726125 ps
CPU time 0.69 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151235801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.2151235801
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.756823512
Short name T711
Test name
Test status
Simulation time 634997573 ps
CPU time 1.04 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756823512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.756823512
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.415467526
Short name T710
Test name
Test status
Simulation time 61322979 ps
CPU time 0.85 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415467526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.415467526
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.2958255368
Short name T707
Test name
Test status
Simulation time 49569126 ps
CPU time 0.89 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958255368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2958255368
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.2398569652
Short name T709
Test name
Test status
Simulation time 55049495 ps
CPU time 0.79 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398569652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.2398569652
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.4264107820
Short name T702
Test name
Test status
Simulation time 100661106 ps
CPU time 0.87 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264107820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.4264107820
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.4185663993
Short name T689
Test name
Test status
Simulation time 135886307 ps
CPU time 0.81 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 208500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185663993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.4185663993
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.1629005132
Short name T714
Test name
Test status
Simulation time 163228182 ps
CPU time 1.07 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629005132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1629005132
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2042243430
Short name T713
Test name
Test status
Simulation time 117421056 ps
CPU time 1.16 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 211140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042243430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.2042243430
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1232758771
Short name T721
Test name
Test status
Simulation time 891281582 ps
CPU time 2.11 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 211292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232758771 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1232758771
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3527932183
Short name T725
Test name
Test status
Simulation time 845584773 ps
CPU time 3.26 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:51 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527932183 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3527932183
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.557259858
Short name T706
Test name
Test status
Simulation time 132948717 ps
CPU time 0.99 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557259858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.557259858
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.3936969593
Short name T690
Test name
Test status
Simulation time 31700635 ps
CPU time 0.8 seconds
Started Feb 09 02:06:38 PM UTC 25
Finished Feb 09 02:06:41 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936969593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3936969593
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.76170152
Short name T723
Test name
Test status
Simulation time 1413440397 ps
CPU time 2.54 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:51 PM UTC 25
Peak memory 211592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76170152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.76170152
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.2291739452
Short name T751
Test name
Test status
Simulation time 9570228738 ps
CPU time 13.61 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:07:02 PM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2291739452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand
_reset.2291739452
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.2199071742
Short name T705
Test name
Test status
Simulation time 298405866 ps
CPU time 1.08 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199071742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.2199071742
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.60484952
Short name T701
Test name
Test status
Simulation time 94323984 ps
CPU time 0.78 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:49 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60484952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.60484952
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.1804425922
Short name T719
Test name
Test status
Simulation time 44690654 ps
CPU time 0.99 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804425922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1804425922
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2536531509
Short name T731
Test name
Test status
Simulation time 56875431 ps
CPU time 0.8 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 210720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536531509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.2536531509
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3179369503
Short name T728
Test name
Test status
Simulation time 64706535 ps
CPU time 0.7 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179369503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.3179369503
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.753364533
Short name T733
Test name
Test status
Simulation time 159535175 ps
CPU time 1.07 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753364533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.753364533
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1762532248
Short name T726
Test name
Test status
Simulation time 75386775 ps
CPU time 0.63 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762532248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1762532248
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.4035529924
Short name T727
Test name
Test status
Simulation time 25469789 ps
CPU time 0.64 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035529924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.4035529924
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.291517465
Short name T735
Test name
Test status
Simulation time 55452948 ps
CPU time 0.87 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291517465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.291517465
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.3311217214
Short name T716
Test name
Test status
Simulation time 192479106 ps
CPU time 0.93 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311217214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.3311217214
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.1895958820
Short name T717
Test name
Test status
Simulation time 130248742 ps
CPU time 1.01 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 208452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895958820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1895958820
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.903765118
Short name T732
Test name
Test status
Simulation time 115787351 ps
CPU time 0.9 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 220200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903765118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.903765118
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.798069226
Short name T729
Test name
Test status
Simulation time 51176630 ps
CPU time 0.66 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798069226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.798069226
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.526551506
Short name T724
Test name
Test status
Simulation time 848329397 ps
CPU time 2.22 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:51 PM UTC 25
Peak memory 211584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526551506 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.526551506
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1789919429
Short name T722
Test name
Test status
Simulation time 1020505287 ps
CPU time 2.04 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:51 PM UTC 25
Peak memory 211184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789919429 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1789919429
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.97848998
Short name T720
Test name
Test status
Simulation time 69352077 ps
CPU time 1.01 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97848998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.97848998
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.2082079022
Short name T712
Test name
Test status
Simulation time 29231172 ps
CPU time 0.75 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082079022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2082079022
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3080946448
Short name T750
Test name
Test status
Simulation time 1086010657 ps
CPU time 3.12 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:07:00 PM UTC 25
Peak memory 211352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080946448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.3080946448
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1098864152
Short name T774
Test name
Test status
Simulation time 27091860590 ps
CPU time 12.8 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:07:10 PM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1098864152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand
_reset.1098864152
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.1800314187
Short name T718
Test name
Test status
Simulation time 180579863 ps
CPU time 1.01 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800314187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.1800314187
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.3250188572
Short name T715
Test name
Test status
Simulation time 53983660 ps
CPU time 0.91 seconds
Started Feb 09 02:06:47 PM UTC 25
Finished Feb 09 02:06:50 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250188572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.3250188572
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.2120710335
Short name T737
Test name
Test status
Simulation time 67994510 ps
CPU time 0.91 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120710335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.2120710335
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.148934583
Short name T743
Test name
Test status
Simulation time 89686902 ps
CPU time 0.77 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148934583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.148934583
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1316010449
Short name T741
Test name
Test status
Simulation time 28609993 ps
CPU time 0.82 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 206456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316010449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.1316010449
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.922334993
Short name T747
Test name
Test status
Simulation time 317165074 ps
CPU time 1.09 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922334993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.922334993
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.3711747450
Short name T739
Test name
Test status
Simulation time 24280672 ps
CPU time 0.65 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711747450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.3711747450
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.1485189134
Short name T734
Test name
Test status
Simulation time 42283510 ps
CPU time 0.69 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485189134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1485189134
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.2941023439
Short name T752
Test name
Test status
Simulation time 73054248 ps
CPU time 0.64 seconds
Started Feb 09 02:07:03 PM UTC 25
Finished Feb 09 02:07:05 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941023439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.2941023439
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.4163594963
Short name T744
Test name
Test status
Simulation time 355706227 ps
CPU time 1.22 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163594963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.4163594963
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.1277938272
Short name T742
Test name
Test status
Simulation time 104000233 ps
CPU time 1.14 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277938272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1277938272
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.2595471028
Short name T755
Test name
Test status
Simulation time 107300793 ps
CPU time 1.07 seconds
Started Feb 09 02:07:03 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595471028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2595471028
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.35670312
Short name T746
Test name
Test status
Simulation time 328487800 ps
CPU time 1.11 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35670312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.35670312
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.141989802
Short name T749
Test name
Test status
Simulation time 1032612281 ps
CPU time 2.21 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:07:00 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141989802 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.141989802
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3336203979
Short name T748
Test name
Test status
Simulation time 1716557217 ps
CPU time 1.69 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 210732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336203979 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3336203979
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.358047241
Short name T745
Test name
Test status
Simulation time 64831538 ps
CPU time 1.11 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:59 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358047241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.358047241
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.2776966437
Short name T730
Test name
Test status
Simulation time 26426463 ps
CPU time 0.72 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776966437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2776966437
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3496968815
Short name T772
Test name
Test status
Simulation time 1513224151 ps
CPU time 2.64 seconds
Started Feb 09 02:07:03 PM UTC 25
Finished Feb 09 02:07:07 PM UTC 25
Peak memory 211340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496968815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.3496968815
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3798121003
Short name T142
Test name
Test status
Simulation time 5592539453 ps
CPU time 10.46 seconds
Started Feb 09 02:07:03 PM UTC 25
Finished Feb 09 02:07:15 PM UTC 25
Peak memory 211884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3798121003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand
_reset.3798121003
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.4161556758
Short name T738
Test name
Test status
Simulation time 152343229 ps
CPU time 1 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161556758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.4161556758
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.2381013790
Short name T740
Test name
Test status
Simulation time 88531554 ps
CPU time 0.93 seconds
Started Feb 09 02:06:56 PM UTC 25
Finished Feb 09 02:06:58 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381013790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2381013790
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.3425814639
Short name T754
Test name
Test status
Simulation time 115414596 ps
CPU time 0.71 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425814639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.3425814639
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.2569794440
Short name T765
Test name
Test status
Simulation time 47212780 ps
CPU time 1.03 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569794440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.2569794440
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.659402498
Short name T756
Test name
Test status
Simulation time 28655057 ps
CPU time 0.77 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659402498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.659402498
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.741163318
Short name T766
Test name
Test status
Simulation time 309956730 ps
CPU time 1.1 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 206436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741163318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.741163318
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.2187362090
Short name T761
Test name
Test status
Simulation time 39590138 ps
CPU time 0.84 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187362090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.2187362090
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3770543809
Short name T758
Test name
Test status
Simulation time 53558744 ps
CPU time 0.7 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770543809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3770543809
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.458200301
Short name T760
Test name
Test status
Simulation time 40165237 ps
CPU time 0.67 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458200301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.458200301
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.2114468465
Short name T759
Test name
Test status
Simulation time 233647604 ps
CPU time 1 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114468465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.2114468465
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1206337821
Short name T757
Test name
Test status
Simulation time 25689433 ps
CPU time 1 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206337821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1206337821
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.988233979
Short name T769
Test name
Test status
Simulation time 108937227 ps
CPU time 1.2 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:07 PM UTC 25
Peak memory 220148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988233979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.988233979
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.1284353202
Short name T768
Test name
Test status
Simulation time 459635937 ps
CPU time 1.23 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 210088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284353202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.1284353202
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3630887594
Short name T773
Test name
Test status
Simulation time 838226609 ps
CPU time 3.03 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:08 PM UTC 25
Peak memory 211724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630887594 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3630887594
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1541137213
Short name T770
Test name
Test status
Simulation time 1114611306 ps
CPU time 2.14 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:07 PM UTC 25
Peak memory 210772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541137213 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1541137213
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2753922651
Short name T763
Test name
Test status
Simulation time 62397526 ps
CPU time 1 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753922651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2753922651
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.545493352
Short name T753
Test name
Test status
Simulation time 35535687 ps
CPU time 0.71 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545493352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.545493352
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.2254945681
Short name T764
Test name
Test status
Simulation time 42192154 ps
CPU time 0.78 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254945681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.2254945681
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.3412053054
Short name T792
Test name
Test status
Simulation time 26165949794 ps
CPU time 13.94 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:19 PM UTC 25
Peak memory 211692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3412053054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand
_reset.3412053054
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.2440640313
Short name T762
Test name
Test status
Simulation time 130472821 ps
CPU time 1.19 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440640313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.2440640313
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.1766022277
Short name T767
Test name
Test status
Simulation time 309449387 ps
CPU time 1.43 seconds
Started Feb 09 02:07:04 PM UTC 25
Finished Feb 09 02:07:06 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766022277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.1766022277
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.224225650
Short name T150
Test name
Test status
Simulation time 61090861 ps
CPU time 0.74 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 211136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224225650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.224225650
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.1059340669
Short name T782
Test name
Test status
Simulation time 67916063 ps
CPU time 1.02 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 210548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059340669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.1059340669
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.777332498
Short name T152
Test name
Test status
Simulation time 30139510 ps
CPU time 0.78 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777332498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.777332498
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.3068481250
Short name T775
Test name
Test status
Simulation time 1084691886 ps
CPU time 1.01 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068481250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3068481250
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.4028192572
Short name T779
Test name
Test status
Simulation time 60670371 ps
CPU time 0.94 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 206364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028192572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.4028192572
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.3879530315
Short name T153
Test name
Test status
Simulation time 22561022 ps
CPU time 0.7 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879530315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.3879530315
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.296673916
Short name T776
Test name
Test status
Simulation time 42716848 ps
CPU time 0.7 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296673916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.296673916
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.1436219426
Short name T149
Test name
Test status
Simulation time 234370841 ps
CPU time 0.79 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436219426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.1436219426
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.3589136730
Short name T148
Test name
Test status
Simulation time 61927254 ps
CPU time 0.77 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589136730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3589136730
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.3324913422
Short name T154
Test name
Test status
Simulation time 152560693 ps
CPU time 0.84 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324913422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3324913422
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.4159124771
Short name T155
Test name
Test status
Simulation time 304872379 ps
CPU time 1.01 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159124771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.4159124771
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3871448892
Short name T789
Test name
Test status
Simulation time 796356624 ps
CPU time 3.45 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:19 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871448892 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3871448892
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2723684831
Short name T786
Test name
Test status
Simulation time 2974451435 ps
CPU time 1.92 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:17 PM UTC 25
Peak memory 210732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723684831 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2723684831
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1740568020
Short name T777
Test name
Test status
Simulation time 88846812 ps
CPU time 1.14 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740568020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1740568020
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.1181838508
Short name T147
Test name
Test status
Simulation time 29789126 ps
CPU time 0.71 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:15 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181838508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1181838508
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.2410044556
Short name T790
Test name
Test status
Simulation time 2125075279 ps
CPU time 3.43 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:19 PM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410044556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.2410044556
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.4098431748
Short name T846
Test name
Test status
Simulation time 9686200427 ps
CPU time 30.8 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:47 PM UTC 25
Peak memory 211632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4098431748 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand
_reset.4098431748
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.1733746968
Short name T151
Test name
Test status
Simulation time 344148660 ps
CPU time 0.94 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733746968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.1733746968
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.1853180850
Short name T778
Test name
Test status
Simulation time 273085882 ps
CPU time 1.25 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853180850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1853180850
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.2270495937
Short name T784
Test name
Test status
Simulation time 80220426 ps
CPU time 0.86 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:17 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270495937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2270495937
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.217231046
Short name T736
Test name
Test status
Simulation time 84234582 ps
CPU time 0.79 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217231046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.217231046
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2261940964
Short name T793
Test name
Test status
Simulation time 38582673 ps
CPU time 0.55 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261940964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.2261940964
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1529113571
Short name T803
Test name
Test status
Simulation time 605784600 ps
CPU time 1.23 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529113571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1529113571
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.1141558640
Short name T796
Test name
Test status
Simulation time 47790510 ps
CPU time 0.71 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141558640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1141558640
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.2731823359
Short name T794
Test name
Test status
Simulation time 40458737 ps
CPU time 0.64 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731823359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2731823359
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.4032290458
Short name T795
Test name
Test status
Simulation time 75041629 ps
CPU time 0.7 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032290458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.4032290458
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.676117327
Short name T783
Test name
Test status
Simulation time 218814187 ps
CPU time 0.94 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:17 PM UTC 25
Peak memory 208428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676117327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.676117327
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.3856559639
Short name T781
Test name
Test status
Simulation time 128674319 ps
CPU time 0.73 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856559639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3856559639
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3219129396
Short name T802
Test name
Test status
Simulation time 143204390 ps
CPU time 0.85 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219129396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3219129396
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.995262342
Short name T799
Test name
Test status
Simulation time 394137631 ps
CPU time 1.06 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995262342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.995262342
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2078816814
Short name T791
Test name
Test status
Simulation time 865904294 ps
CPU time 3.37 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:19 PM UTC 25
Peak memory 211388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078816814 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2078816814
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2749901362
Short name T788
Test name
Test status
Simulation time 1243547678 ps
CPU time 2.16 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:18 PM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749901362 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2749901362
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174305598
Short name T798
Test name
Test status
Simulation time 108527338 ps
CPU time 1.04 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174305598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174305598
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.4008376276
Short name T780
Test name
Test status
Simulation time 39548755 ps
CPU time 0.77 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:16 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008376276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.4008376276
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.2602140456
Short name T808
Test name
Test status
Simulation time 260602302 ps
CPU time 1.17 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 211196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602140456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.2602140456
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1658223685
Short name T156
Test name
Test status
Simulation time 1952369425 ps
CPU time 7.2 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:34 PM UTC 25
Peak memory 211524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1658223685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand
_reset.1658223685
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.4205938255
Short name T787
Test name
Test status
Simulation time 279668159 ps
CPU time 1.36 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:17 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205938255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.4205938255
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.367920111
Short name T785
Test name
Test status
Simulation time 194361315 ps
CPU time 0.92 seconds
Started Feb 09 02:07:14 PM UTC 25
Finished Feb 09 02:07:17 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367920111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.367920111
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.2549484726
Short name T809
Test name
Test status
Simulation time 35374726 ps
CPU time 0.81 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549484726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.2549484726
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.970261276
Short name T811
Test name
Test status
Simulation time 70077126 ps
CPU time 0.66 seconds
Started Feb 09 02:07:26 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970261276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.970261276
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4207666586
Short name T807
Test name
Test status
Simulation time 31963683 ps
CPU time 0.82 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207666586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.4207666586
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.1368145858
Short name T817
Test name
Test status
Simulation time 160575675 ps
CPU time 1.01 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368145858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1368145858
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.900549864
Short name T805
Test name
Test status
Simulation time 29300739 ps
CPU time 0.67 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 206404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900549864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.900549864
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2548429297
Short name T812
Test name
Test status
Simulation time 28041430 ps
CPU time 0.78 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548429297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2548429297
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.1016314638
Short name T815
Test name
Test status
Simulation time 52348711 ps
CPU time 0.77 seconds
Started Feb 09 02:07:26 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016314638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.1016314638
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.899723074
Short name T801
Test name
Test status
Simulation time 154765331 ps
CPU time 0.85 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899723074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.899723074
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.2020035249
Short name T806
Test name
Test status
Simulation time 41818322 ps
CPU time 0.89 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020035249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2020035249
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1774704858
Short name T813
Test name
Test status
Simulation time 182768676 ps
CPU time 0.76 seconds
Started Feb 09 02:07:26 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774704858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.1774704858
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.2503888503
Short name T810
Test name
Test status
Simulation time 286984613 ps
CPU time 0.9 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503888503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.2503888503
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379002443
Short name T819
Test name
Test status
Simulation time 827626216 ps
CPU time 2.95 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:30 PM UTC 25
Peak memory 211524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379002443 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.379002443
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3553750990
Short name T818
Test name
Test status
Simulation time 1242607752 ps
CPU time 2.16 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:29 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553750990 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3553750990
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2719125192
Short name T816
Test name
Test status
Simulation time 54040768 ps
CPU time 1.04 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719125192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2719125192
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.1025354612
Short name T797
Test name
Test status
Simulation time 52889733 ps
CPU time 0.65 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:27 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025354612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1025354612
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.654166829
Short name T844
Test name
Test status
Simulation time 1135727091 ps
CPU time 4.07 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:42 PM UTC 25
Peak memory 211368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654166829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.654166829
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.2329693935
Short name T847
Test name
Test status
Simulation time 3750835440 ps
CPU time 10.97 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:49 PM UTC 25
Peak memory 211664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2329693935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand
_reset.2329693935
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.2544390303
Short name T804
Test name
Test status
Simulation time 44548738 ps
CPU time 0.73 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544390303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.2544390303
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.987747977
Short name T814
Test name
Test status
Simulation time 824157535 ps
CPU time 1.21 seconds
Started Feb 09 02:07:25 PM UTC 25
Finished Feb 09 02:07:28 PM UTC 25
Peak memory 210708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987747977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.987747977
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1711920600
Short name T107
Test name
Test status
Simulation time 42158220 ps
CPU time 1.25 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 208340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711920600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1711920600
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2284042263
Short name T160
Test name
Test status
Simulation time 30794053 ps
CPU time 0.79 seconds
Started Feb 09 02:03:56 PM UTC 25
Finished Feb 09 02:03:58 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284042263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.2284042263
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.1436833449
Short name T132
Test name
Test status
Simulation time 168977353 ps
CPU time 1.62 seconds
Started Feb 09 02:03:56 PM UTC 25
Finished Feb 09 02:03:59 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436833449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.1436833449
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.647452803
Short name T134
Test name
Test status
Simulation time 64443469 ps
CPU time 0.98 seconds
Started Feb 09 02:03:57 PM UTC 25
Finished Feb 09 02:04:00 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647452803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.647452803
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.103359976
Short name T210
Test name
Test status
Simulation time 233230143 ps
CPU time 0.9 seconds
Started Feb 09 02:03:56 PM UTC 25
Finished Feb 09 02:03:58 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103359976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.103359976
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.1605677762
Short name T138
Test name
Test status
Simulation time 57066773 ps
CPU time 0.83 seconds
Started Feb 09 02:03:59 PM UTC 25
Finished Feb 09 02:04:01 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605677762 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.1605677762
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.4016412452
Short name T209
Test name
Test status
Simulation time 216574209 ps
CPU time 1.42 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016412452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.4016412452
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.3553602008
Short name T207
Test name
Test status
Simulation time 99788573 ps
CPU time 1.09 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 208504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553602008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3553602008
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.192050412
Short name T135
Test name
Test status
Simulation time 130360952 ps
CPU time 1 seconds
Started Feb 09 02:03:57 PM UTC 25
Finished Feb 09 02:04:00 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192050412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.192050412
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.234444695
Short name T31
Test name
Test status
Simulation time 452485337 ps
CPU time 1.4 seconds
Started Feb 09 02:03:59 PM UTC 25
Finished Feb 09 02:04:01 PM UTC 25
Peak memory 236872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234444695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.234444695
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.954912260
Short name T211
Test name
Test status
Simulation time 123775657 ps
CPU time 1.19 seconds
Started Feb 09 02:03:56 PM UTC 25
Finished Feb 09 02:03:59 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954912260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.954912260
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2276615945
Short name T136
Test name
Test status
Simulation time 749785093 ps
CPU time 3.46 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:04:00 PM UTC 25
Peak memory 211644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276615945 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2276615945
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2970152814
Short name T137
Test name
Test status
Simulation time 2071155491 ps
CPU time 2.58 seconds
Started Feb 09 02:03:56 PM UTC 25
Finished Feb 09 02:04:00 PM UTC 25
Peak memory 211360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970152814 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2970152814
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2152323756
Short name T212
Test name
Test status
Simulation time 170330528 ps
CPU time 1.28 seconds
Started Feb 09 02:03:56 PM UTC 25
Finished Feb 09 02:03:59 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152323756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2152323756
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.1769136412
Short name T205
Test name
Test status
Simulation time 41884168 ps
CPU time 0.96 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769136412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1769136412
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.711625985
Short name T221
Test name
Test status
Simulation time 635204581 ps
CPU time 2.87 seconds
Started Feb 09 02:03:59 PM UTC 25
Finished Feb 09 02:04:03 PM UTC 25
Peak memory 211372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711625985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.711625985
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3314611975
Short name T25
Test name
Test status
Simulation time 3861477542 ps
CPU time 9.31 seconds
Started Feb 09 02:03:59 PM UTC 25
Finished Feb 09 02:04:09 PM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3314611975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_
reset.3314611975
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.912998740
Short name T208
Test name
Test status
Simulation time 148641623 ps
CPU time 1.08 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912998740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.912998740
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3703185680
Short name T206
Test name
Test status
Simulation time 208767910 ps
CPU time 0.9 seconds
Started Feb 09 02:03:55 PM UTC 25
Finished Feb 09 02:03:57 PM UTC 25
Peak memory 210892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703185680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3703185680
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1131300252
Short name T830
Test name
Test status
Simulation time 77266842 ps
CPU time 0.99 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131300252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1131300252
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.2241866677
Short name T832
Test name
Test status
Simulation time 58196740 ps
CPU time 0.92 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241866677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.2241866677
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.700344829
Short name T825
Test name
Test status
Simulation time 38658031 ps
CPU time 0.58 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700344829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.700344829
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.3032791615
Short name T833
Test name
Test status
Simulation time 157998718 ps
CPU time 1.08 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032791615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3032791615
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.4147600844
Short name T826
Test name
Test status
Simulation time 190194495 ps
CPU time 0.64 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147600844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.4147600844
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.4086588146
Short name T827
Test name
Test status
Simulation time 106135746 ps
CPU time 0.66 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 206404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086588146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.4086588146
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.3693468268
Short name T831
Test name
Test status
Simulation time 81775613 ps
CPU time 0.83 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693468268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.3693468268
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.1818411884
Short name T823
Test name
Test status
Simulation time 29221977 ps
CPU time 0.73 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:38 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818411884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.1818411884
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.232782350
Short name T821
Test name
Test status
Simulation time 45755479 ps
CPU time 0.82 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:38 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232782350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.232782350
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.2249619909
Short name T834
Test name
Test status
Simulation time 103467277 ps
CPU time 1.06 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249619909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.2249619909
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.1878295738
Short name T836
Test name
Test status
Simulation time 258894591 ps
CPU time 1.35 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878295738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.1878295738
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4200333590
Short name T841
Test name
Test status
Simulation time 1045485685 ps
CPU time 1.93 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:40 PM UTC 25
Peak memory 210700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200333590 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4200333590
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3627770980
Short name T842
Test name
Test status
Simulation time 1168373490 ps
CPU time 2.14 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:40 PM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627770980 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3627770980
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.779536181
Short name T828
Test name
Test status
Simulation time 131632621 ps
CPU time 0.85 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779536181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.779536181
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3312981059
Short name T820
Test name
Test status
Simulation time 36221006 ps
CPU time 0.71 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:38 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312981059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3312981059
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.2881352483
Short name T845
Test name
Test status
Simulation time 1395796749 ps
CPU time 3.47 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:42 PM UTC 25
Peak memory 211280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881352483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.2881352483
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.4226075390
Short name T75
Test name
Test status
Simulation time 7218624703 ps
CPU time 11.39 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 211528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4226075390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand
_reset.4226075390
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.2844732384
Short name T822
Test name
Test status
Simulation time 32048561 ps
CPU time 0.69 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:38 PM UTC 25
Peak memory 208528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844732384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.2844732384
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.995594805
Short name T824
Test name
Test status
Simulation time 52558123 ps
CPU time 0.76 seconds
Started Feb 09 02:07:36 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995594805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.995594805
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.3483325303
Short name T840
Test name
Test status
Simulation time 64703291 ps
CPU time 1.08 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:40 PM UTC 25
Peak memory 211144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483325303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3483325303
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.2107811978
Short name T857
Test name
Test status
Simulation time 77106695 ps
CPU time 1.09 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107811978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.2107811978
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.2949459422
Short name T848
Test name
Test status
Simulation time 69034137 ps
CPU time 0.53 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 206452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949459422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.2949459422
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2235595756
Short name T853
Test name
Test status
Simulation time 237985905 ps
CPU time 1 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235595756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2235595756
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2851578805
Short name T850
Test name
Test status
Simulation time 57855802 ps
CPU time 0.6 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851578805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2851578805
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.3850110823
Short name T849
Test name
Test status
Simulation time 72444592 ps
CPU time 0.68 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850110823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3850110823
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.357247509
Short name T852
Test name
Test status
Simulation time 98914690 ps
CPU time 0.69 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 211064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357247509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.357247509
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.861334368
Short name T839
Test name
Test status
Simulation time 118833284 ps
CPU time 1.09 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:40 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861334368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.861334368
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.1898740546
Short name T837
Test name
Test status
Simulation time 30910621 ps
CPU time 0.92 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898740546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1898740546
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1887579397
Short name T858
Test name
Test status
Simulation time 117069750 ps
CPU time 0.99 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887579397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1887579397
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.2990345073
Short name T856
Test name
Test status
Simulation time 117242073 ps
CPU time 1.2 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990345073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.2990345073
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2239293417
Short name T843
Test name
Test status
Simulation time 927457279 ps
CPU time 2.32 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:41 PM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239293417 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2239293417
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2126838538
Short name T869
Test name
Test status
Simulation time 1401095658 ps
CPU time 2.17 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 211652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126838538 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2126838538
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.523980371
Short name T851
Test name
Test status
Simulation time 151067878 ps
CPU time 0.88 seconds
Started Feb 09 02:07:47 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523980371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.523980371
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.701161578
Short name T829
Test name
Test status
Simulation time 51090902 ps
CPU time 0.78 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701161578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.701161578
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.2048313388
Short name T872
Test name
Test status
Simulation time 1748693383 ps
CPU time 3.51 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:53 PM UTC 25
Peak memory 211368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048313388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.2048313388
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.3175397022
Short name T143
Test name
Test status
Simulation time 8070399913 ps
CPU time 26.55 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 211884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3175397022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand
_reset.3175397022
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.1308692754
Short name T835
Test name
Test status
Simulation time 179209357 ps
CPU time 0.8 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 208512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308692754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.1308692754
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.2745410604
Short name T838
Test name
Test status
Simulation time 208619144 ps
CPU time 0.97 seconds
Started Feb 09 02:07:37 PM UTC 25
Finished Feb 09 02:07:39 PM UTC 25
Peak memory 211480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745410604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.2745410604
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.598584644
Short name T862
Test name
Test status
Simulation time 18619131 ps
CPU time 0.7 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598584644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.598584644
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.4030744834
Short name T863
Test name
Test status
Simulation time 86846892 ps
CPU time 0.69 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030744834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.4030744834
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4175618096
Short name T865
Test name
Test status
Simulation time 101119980 ps
CPU time 0.58 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175618096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.4175618096
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.2335037043
Short name T868
Test name
Test status
Simulation time 799262468 ps
CPU time 1.06 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 206296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335037043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.2335037043
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.4112904130
Short name T867
Test name
Test status
Simulation time 36090965 ps
CPU time 0.58 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112904130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.4112904130
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.3684803994
Short name T866
Test name
Test status
Simulation time 49134202 ps
CPU time 0.63 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684803994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.3684803994
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.2930638929
Short name T875
Test name
Test status
Simulation time 55784892 ps
CPU time 0.78 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:02 PM UTC 25
Peak memory 211064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930638929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.2930638929
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3309646640
Short name T860
Test name
Test status
Simulation time 159884185 ps
CPU time 0.88 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309646640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.3309646640
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.2470319369
Short name T800
Test name
Test status
Simulation time 71257500 ps
CPU time 0.83 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470319369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2470319369
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1729571157
Short name T873
Test name
Test status
Simulation time 163354465 ps
CPU time 0.75 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:02 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729571157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1729571157
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.979082146
Short name T864
Test name
Test status
Simulation time 163066788 ps
CPU time 0.75 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 208364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979082146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.979082146
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2416511290
Short name T870
Test name
Test status
Simulation time 2047675023 ps
CPU time 1.91 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:52 PM UTC 25
Peak memory 210700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416511290 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2416511290
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1300846378
Short name T871
Test name
Test status
Simulation time 1052609155 ps
CPU time 2.46 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:52 PM UTC 25
Peak memory 211436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300846378 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1300846378
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.68190690
Short name T859
Test name
Test status
Simulation time 54089052 ps
CPU time 0.88 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:51 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68190690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.68190690
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.3220818989
Short name T861
Test name
Test status
Simulation time 39952204 ps
CPU time 0.83 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220818989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.3220818989
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.2620169777
Short name T901
Test name
Test status
Simulation time 1073526275 ps
CPU time 3.91 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:06 PM UTC 25
Peak memory 211348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620169777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2620169777
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.2124743657
Short name T930
Test name
Test status
Simulation time 9516665854 ps
CPU time 17.13 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:19 PM UTC 25
Peak memory 211968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2124743657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand
_reset.2124743657
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2559811524
Short name T854
Test name
Test status
Simulation time 80831143 ps
CPU time 0.74 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559811524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2559811524
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.4054041187
Short name T855
Test name
Test status
Simulation time 68035302 ps
CPU time 0.63 seconds
Started Feb 09 02:07:48 PM UTC 25
Finished Feb 09 02:07:50 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054041187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.4054041187
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.2815336728
Short name T876
Test name
Test status
Simulation time 20521965 ps
CPU time 0.72 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:02 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815336728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2815336728
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.3653043989
Short name T885
Test name
Test status
Simulation time 103953865 ps
CPU time 0.75 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 210720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653043989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.3653043989
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3968326695
Short name T886
Test name
Test status
Simulation time 39496228 ps
CPU time 0.8 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968326695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.3968326695
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2227607633
Short name T890
Test name
Test status
Simulation time 302182472 ps
CPU time 0.98 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227607633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2227607633
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.3094610417
Short name T882
Test name
Test status
Simulation time 38606398 ps
CPU time 0.64 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094610417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3094610417
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3766756074
Short name T880
Test name
Test status
Simulation time 65193458 ps
CPU time 0.57 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766756074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3766756074
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.977617212
Short name T891
Test name
Test status
Simulation time 47543439 ps
CPU time 0.91 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977617212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.977617212
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.769167978
Short name T881
Test name
Test status
Simulation time 166271080 ps
CPU time 1.06 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769167978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.769167978
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.3305466378
Short name T878
Test name
Test status
Simulation time 109264162 ps
CPU time 0.78 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305466378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.3305466378
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.74480096
Short name T888
Test name
Test status
Simulation time 161129232 ps
CPU time 0.88 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 220272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74480096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.74480096
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3126197578
Short name T895
Test name
Test status
Simulation time 276235383 ps
CPU time 1.32 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126197578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.3126197578
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2363620234
Short name T900
Test name
Test status
Simulation time 869792301 ps
CPU time 2.84 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:05 PM UTC 25
Peak memory 211408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363620234 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2363620234
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.481314222
Short name T898
Test name
Test status
Simulation time 1156353020 ps
CPU time 2.17 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 211184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481314222 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.481314222
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4241488791
Short name T884
Test name
Test status
Simulation time 79019773 ps
CPU time 0.88 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241488791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4241488791
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.1624783920
Short name T877
Test name
Test status
Simulation time 82714442 ps
CPU time 0.72 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624783920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.1624783920
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.1460332491
Short name T897
Test name
Test status
Simulation time 334085901 ps
CPU time 1.25 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 211260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460332491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.1460332491
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.534411446
Short name T144
Test name
Test status
Simulation time 8940445283 ps
CPU time 27.06 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:30 PM UTC 25
Peak memory 211708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=534411446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_
reset.534411446
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.3159272747
Short name T894
Test name
Test status
Simulation time 217463775 ps
CPU time 1.71 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159272747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.3159272747
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.2264957300
Short name T883
Test name
Test status
Simulation time 470947389 ps
CPU time 1.14 seconds
Started Feb 09 02:08:00 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264957300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.2264957300
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3738119854
Short name T892
Test name
Test status
Simulation time 35984506 ps
CPU time 0.77 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738119854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3738119854
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.797410387
Short name T909
Test name
Test status
Simulation time 55117263 ps
CPU time 0.89 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797410387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.797410387
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1644053243
Short name T904
Test name
Test status
Simulation time 31463218 ps
CPU time 0.62 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:15 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644053243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.1644053243
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.1703063180
Short name T910
Test name
Test status
Simulation time 190657052 ps
CPU time 1 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703063180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.1703063180
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.2463150759
Short name T905
Test name
Test status
Simulation time 138705392 ps
CPU time 0.55 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:15 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463150759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2463150759
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.2717874593
Short name T903
Test name
Test status
Simulation time 224527947 ps
CPU time 0.58 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:15 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717874593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2717874593
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.3087049072
Short name T906
Test name
Test status
Simulation time 76712937 ps
CPU time 0.72 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087049072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.3087049072
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1725706282
Short name T887
Test name
Test status
Simulation time 83831095 ps
CPU time 0.66 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725706282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.1725706282
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.444016592
Short name T893
Test name
Test status
Simulation time 42261618 ps
CPU time 0.95 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444016592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.444016592
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.621847374
Short name T914
Test name
Test status
Simulation time 154751026 ps
CPU time 1.22 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 220200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621847374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.621847374
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.627392040
Short name T908
Test name
Test status
Simulation time 307478590 ps
CPU time 1 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627392040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.627392040
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2649422256
Short name T902
Test name
Test status
Simulation time 797575635 ps
CPU time 2.23 seconds
Started Feb 09 02:08:02 PM UTC 25
Finished Feb 09 02:08:06 PM UTC 25
Peak memory 211616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649422256 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2649422256
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590009698
Short name T929
Test name
Test status
Simulation time 889706375 ps
CPU time 3.4 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:18 PM UTC 25
Peak memory 211440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590009698 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3590009698
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.578058585
Short name T907
Test name
Test status
Simulation time 89280219 ps
CPU time 0.94 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578058585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.578058585
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.2455039445
Short name T889
Test name
Test status
Simulation time 99332584 ps
CPU time 0.69 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:03 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455039445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2455039445
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.284457331
Short name T931
Test name
Test status
Simulation time 2056834514 ps
CPU time 6.5 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:22 PM UTC 25
Peak memory 211436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284457331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.284457331
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.972482684
Short name T932
Test name
Test status
Simulation time 3341114701 ps
CPU time 7.98 seconds
Started Feb 09 02:08:13 PM UTC 25
Finished Feb 09 02:08:23 PM UTC 25
Peak memory 211916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=972482684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_
reset.972482684
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.2431456175
Short name T896
Test name
Test status
Simulation time 103457464 ps
CPU time 0.95 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431456175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.2431456175
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1752343592
Short name T899
Test name
Test status
Simulation time 269601690 ps
CPU time 1.53 seconds
Started Feb 09 02:08:01 PM UTC 25
Finished Feb 09 02:08:04 PM UTC 25
Peak memory 210956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752343592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.1752343592
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.2810640333
Short name T920
Test name
Test status
Simulation time 61994420 ps
CPU time 1.2 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810640333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2810640333
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.79638156
Short name T923
Test name
Test status
Simulation time 164461537 ps
CPU time 0.82 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 210832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79638156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.79638156
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.1343802376
Short name T913
Test name
Test status
Simulation time 55326460 ps
CPU time 0.73 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343802376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.1343802376
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.1683181886
Short name T922
Test name
Test status
Simulation time 161282395 ps
CPU time 0.99 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683181886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1683181886
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.3885265616
Short name T921
Test name
Test status
Simulation time 52737198 ps
CPU time 0.71 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885265616 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3885265616
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.1215744012
Short name T918
Test name
Test status
Simulation time 82954383 ps
CPU time 0.67 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 206400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215744012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1215744012
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.1536238058
Short name T926
Test name
Test status
Simulation time 82786650 ps
CPU time 0.64 seconds
Started Feb 09 02:08:15 PM UTC 25
Finished Feb 09 02:08:17 PM UTC 25
Peak memory 211012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536238058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.1536238058
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.2135524152
Short name T924
Test name
Test status
Simulation time 371263017 ps
CPU time 1.46 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:17 PM UTC 25
Peak memory 208448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135524152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.2135524152
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.371211787
Short name T912
Test name
Test status
Simulation time 62565742 ps
CPU time 0.85 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371211787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.371211787
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1474221284
Short name T925
Test name
Test status
Simulation time 101918642 ps
CPU time 1.01 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:17 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474221284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1474221284
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.2832605891
Short name T919
Test name
Test status
Simulation time 481769224 ps
CPU time 0.85 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832605891 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.2832605891
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3358250035
Short name T928
Test name
Test status
Simulation time 815316243 ps
CPU time 2.93 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:18 PM UTC 25
Peak memory 211724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358250035 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3358250035
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3116836857
Short name T927
Test name
Test status
Simulation time 1162405920 ps
CPU time 2.12 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:17 PM UTC 25
Peak memory 211232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116836857 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3116836857
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3793805143
Short name T916
Test name
Test status
Simulation time 109991922 ps
CPU time 0.97 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793805143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3793805143
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.2543218979
Short name T911
Test name
Test status
Simulation time 50596515 ps
CPU time 0.81 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543218979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2543218979
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.1277561818
Short name T954
Test name
Test status
Simulation time 1558753017 ps
CPU time 3.87 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:31 PM UTC 25
Peak memory 211460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277561818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.1277561818
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2417367642
Short name T65
Test name
Test status
Simulation time 8698448376 ps
CPU time 18.93 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:46 PM UTC 25
Peak memory 211676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2417367642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand
_reset.2417367642
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.4123895275
Short name T915
Test name
Test status
Simulation time 237643564 ps
CPU time 1.1 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123895275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.4123895275
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.1632852457
Short name T917
Test name
Test status
Simulation time 259434958 ps
CPU time 1.06 seconds
Started Feb 09 02:08:14 PM UTC 25
Finished Feb 09 02:08:16 PM UTC 25
Peak memory 210896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632852457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1632852457
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.374424504
Short name T938
Test name
Test status
Simulation time 45196996 ps
CPU time 0.83 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 211196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374424504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.374424504
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.3518223885
Short name T941
Test name
Test status
Simulation time 89255379 ps
CPU time 0.94 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518223885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.3518223885
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3451429033
Short name T935
Test name
Test status
Simulation time 30509876 ps
CPU time 0.6 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451429033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.3451429033
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.3264443539
Short name T944
Test name
Test status
Simulation time 317039901 ps
CPU time 0.98 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 208372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264443539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.3264443539
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.426317559
Short name T874
Test name
Test status
Simulation time 32630611 ps
CPU time 0.67 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426317559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.426317559
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.3277515349
Short name T939
Test name
Test status
Simulation time 44775080 ps
CPU time 0.64 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277515349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3277515349
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.1255216709
Short name T940
Test name
Test status
Simulation time 96482123 ps
CPU time 0.63 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255216709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.1255216709
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.3901940498
Short name T937
Test name
Test status
Simulation time 95645914 ps
CPU time 0.9 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901940498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.3901940498
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3879548312
Short name T934
Test name
Test status
Simulation time 48960209 ps
CPU time 0.84 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879548312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3879548312
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.2948972255
Short name T879
Test name
Test status
Simulation time 150191447 ps
CPU time 0.85 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 220268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948972255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2948972255
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.82668258
Short name T949
Test name
Test status
Simulation time 193696039 ps
CPU time 1.33 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82668258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.82668258
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2837625114
Short name T951
Test name
Test status
Simulation time 1034878163 ps
CPU time 1.97 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:30 PM UTC 25
Peak memory 211252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837625114 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2837625114
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89987866
Short name T952
Test name
Test status
Simulation time 1545976768 ps
CPU time 2.42 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:30 PM UTC 25
Peak memory 211524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89987866 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89987866
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.316902544
Short name T942
Test name
Test status
Simulation time 95965279 ps
CPU time 1.03 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 208456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316902544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.316902544
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2240807342
Short name T933
Test name
Test status
Simulation time 57071653 ps
CPU time 0.73 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240807342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2240807342
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.4008536494
Short name T953
Test name
Test status
Simulation time 468261298 ps
CPU time 2.4 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:31 PM UTC 25
Peak memory 210872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008536494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.4008536494
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4139430612
Short name T86
Test name
Test status
Simulation time 11642144227 ps
CPU time 23.73 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:52 PM UTC 25
Peak memory 211932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4139430612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand
_reset.4139430612
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.2097123430
Short name T936
Test name
Test status
Simulation time 90164090 ps
CPU time 0.82 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:28 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097123430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.2097123430
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.2933102324
Short name T946
Test name
Test status
Simulation time 306952159 ps
CPU time 1.53 seconds
Started Feb 09 02:08:26 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933102324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.2933102324
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.4145374045
Short name T955
Test name
Test status
Simulation time 53745080 ps
CPU time 0.74 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145374045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.4145374045
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1122356734
Short name T187
Test name
Test status
Simulation time 62516822 ps
CPU time 0.7 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 210720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122356734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.1122356734
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3593142592
Short name T957
Test name
Test status
Simulation time 31096993 ps
CPU time 0.73 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593142592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.3593142592
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.2725393242
Short name T962
Test name
Test status
Simulation time 562404416 ps
CPU time 0.94 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725393242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2725393242
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.2003480391
Short name T960
Test name
Test status
Simulation time 41502447 ps
CPU time 0.8 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003480391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2003480391
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.3081649969
Short name T959
Test name
Test status
Simulation time 98242530 ps
CPU time 0.72 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081649969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.3081649969
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.72308181
Short name T961
Test name
Test status
Simulation time 45298819 ps
CPU time 0.74 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72308181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.72308181
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2247172452
Short name T948
Test name
Test status
Simulation time 99967114 ps
CPU time 1 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 207484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247172452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.2247172452
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.1058788557
Short name T947
Test name
Test status
Simulation time 117124699 ps
CPU time 0.92 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 210836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058788557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.1058788557
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.3128536727
Short name T964
Test name
Test status
Simulation time 121117149 ps
CPU time 0.95 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 220328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128536727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3128536727
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.4016989944
Short name T958
Test name
Test status
Simulation time 34982153 ps
CPU time 0.75 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016989944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.4016989944
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815348778
Short name T979
Test name
Test status
Simulation time 872627433 ps
CPU time 3.14 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:43 PM UTC 25
Peak memory 211224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815348778 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2815348778
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.871167435
Short name T976
Test name
Test status
Simulation time 1263130505 ps
CPU time 2.24 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 211312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871167435 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.871167435
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1504066912
Short name T956
Test name
Test status
Simulation time 65287707 ps
CPU time 0.83 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 208284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504066912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1504066912
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.741734247
Short name T943
Test name
Test status
Simulation time 25861472 ps
CPU time 0.7 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741734247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.741734247
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.671929291
Short name T980
Test name
Test status
Simulation time 2325495285 ps
CPU time 3.5 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:44 PM UTC 25
Peak memory 211648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671929291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.671929291
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.250909178
Short name T145
Test name
Test status
Simulation time 11951581593 ps
CPU time 23.59 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:09:04 PM UTC 25
Peak memory 211916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=250909178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_
reset.250909178
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.4128533538
Short name T945
Test name
Test status
Simulation time 180104502 ps
CPU time 0.82 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128533538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.4128533538
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2041365700
Short name T950
Test name
Test status
Simulation time 245014791 ps
CPU time 1.12 seconds
Started Feb 09 02:08:27 PM UTC 25
Finished Feb 09 02:08:29 PM UTC 25
Peak memory 211496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041365700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.2041365700
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.4250355527
Short name T967
Test name
Test status
Simulation time 46848983 ps
CPU time 0.86 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 208400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250355527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.4250355527
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.206756009
Short name T188
Test name
Test status
Simulation time 55515095 ps
CPU time 0.82 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206756009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.206756009
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.115201587
Short name T968
Test name
Test status
Simulation time 37072275 ps
CPU time 0.65 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115201587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.115201587
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.3175843682
Short name T975
Test name
Test status
Simulation time 165484678 ps
CPU time 0.91 seconds
Started Feb 09 02:08:40 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175843682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3175843682
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.1385015232
Short name T971
Test name
Test status
Simulation time 66341645 ps
CPU time 0.68 seconds
Started Feb 09 02:08:40 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 206484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385015232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1385015232
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.974710399
Short name T972
Test name
Test status
Simulation time 49972496 ps
CPU time 0.63 seconds
Started Feb 09 02:08:40 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974710399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_t
est +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.974710399
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.451047688
Short name T981
Test name
Test status
Simulation time 55266623 ps
CPU time 0.72 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 211056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451047688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid.451047688
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.2064494895
Short name T973
Test name
Test status
Simulation time 329979765 ps
CPU time 1.04 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064494895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.2064494895
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.2571090588
Short name T965
Test name
Test status
Simulation time 36647666 ps
CPU time 0.77 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571090588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.2571090588
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.3726534475
Short name T988
Test name
Test status
Simulation time 103147407 ps
CPU time 1.05 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726534475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3726534475
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3722231310
Short name T970
Test name
Test status
Simulation time 46629599 ps
CPU time 0.7 seconds
Started Feb 09 02:08:40 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722231310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.3722231310
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2553042426
Short name T977
Test name
Test status
Simulation time 1239721197 ps
CPU time 2.03 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:43 PM UTC 25
Peak memory 211396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553042426 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2553042426
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163844603
Short name T978
Test name
Test status
Simulation time 839693842 ps
CPU time 2.37 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:43 PM UTC 25
Peak memory 211264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163844603 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163844603
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.286870231
Short name T966
Test name
Test status
Simulation time 142464879 ps
CPU time 0.77 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 208308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286870231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.286870231
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3801454362
Short name T963
Test name
Test status
Simulation time 45628945 ps
CPU time 0.64 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:41 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801454362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3801454362
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1399704833
Short name T1001
Test name
Test status
Simulation time 1544734566 ps
CPU time 6.13 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:59 PM UTC 25
Peak memory 211416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399704833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1399704833
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.425367952
Short name T1003
Test name
Test status
Simulation time 13503244457 ps
CPU time 9.51 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:09:02 PM UTC 25
Peak memory 211576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=425367952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_
reset.425367952
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.3568007295
Short name T974
Test name
Test status
Simulation time 136121510 ps
CPU time 1.03 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 208532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568007295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.3568007295
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.247475980
Short name T969
Test name
Test status
Simulation time 164970724 ps
CPU time 0.79 seconds
Started Feb 09 02:08:39 PM UTC 25
Finished Feb 09 02:08:42 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247475980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.247475980
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2521475743
Short name T986
Test name
Test status
Simulation time 38243538 ps
CPU time 0.69 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521475743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2521475743
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.3868798915
Short name T993
Test name
Test status
Simulation time 56809609 ps
CPU time 0.86 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868798915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.3868798915
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.2162118958
Short name T985
Test name
Test status
Simulation time 38603886 ps
CPU time 0.55 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 206496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162118958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.2162118958
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.966144474
Short name T998
Test name
Test status
Simulation time 714185758 ps
CPU time 1.25 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:55 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966144474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.966144474
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.878868250
Short name T987
Test name
Test status
Simulation time 45329970 ps
CPU time 0.62 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878868250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.878868250
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.3960267037
Short name T990
Test name
Test status
Simulation time 74188478 ps
CPU time 0.68 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960267037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3960267037
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.2625180769
Short name T989
Test name
Test status
Simulation time 77522509 ps
CPU time 0.63 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625180769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.2625180769
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.2337763942
Short name T983
Test name
Test status
Simulation time 84997968 ps
CPU time 0.69 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337763942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.2337763942
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.841462299
Short name T984
Test name
Test status
Simulation time 32387240 ps
CPU time 0.74 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841462299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.841462299
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.2222805349
Short name T996
Test name
Test status
Simulation time 108504068 ps
CPU time 1.17 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:55 PM UTC 25
Peak memory 220208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222805349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.2222805349
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2546326381
Short name T991
Test name
Test status
Simulation time 65152140 ps
CPU time 0.81 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546326381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.2546326381
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1125619826
Short name T999
Test name
Test status
Simulation time 1030718224 ps
CPU time 2.39 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:56 PM UTC 25
Peak memory 211448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125619826 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1125619826
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3254319926
Short name T1000
Test name
Test status
Simulation time 890533180 ps
CPU time 3.21 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:56 PM UTC 25
Peak memory 211296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254319926 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3254319926
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1967280708
Short name T992
Test name
Test status
Simulation time 97864655 ps
CPU time 0.79 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967280708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1967280708
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.4279935334
Short name T982
Test name
Test status
Simulation time 36279790 ps
CPU time 0.74 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:54 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279935334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.4279935334
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.2498988200
Short name T995
Test name
Test status
Simulation time 389781316 ps
CPU time 1.08 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:55 PM UTC 25
Peak memory 210896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498988200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.2498988200
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.2697724591
Short name T1002
Test name
Test status
Simulation time 3035158544 ps
CPU time 7.7 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:09:01 PM UTC 25
Peak memory 211500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=2697724591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand
_reset.2697724591
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.479252256
Short name T994
Test name
Test status
Simulation time 295177917 ps
CPU time 1.33 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:55 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479252256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.479252256
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.4202323287
Short name T997
Test name
Test status
Simulation time 323761273 ps
CPU time 1.53 seconds
Started Feb 09 02:08:52 PM UTC 25
Finished Feb 09 02:08:55 PM UTC 25
Peak memory 210768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202323287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.4202323287
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.305701242
Short name T109
Test name
Test status
Simulation time 21437700 ps
CPU time 0.99 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:03 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305701242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_abo
rted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.305701242
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2967905957
Short name T170
Test name
Test status
Simulation time 62309390 ps
CPU time 1.31 seconds
Started Feb 09 02:04:02 PM UTC 25
Finished Feb 09 02:04:05 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967905957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.2967905957
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.734749384
Short name T218
Test name
Test status
Simulation time 43498889 ps
CPU time 0.82 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:02 PM UTC 25
Peak memory 206488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734749384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.734749384
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.2437073377
Short name T161
Test name
Test status
Simulation time 213473002 ps
CPU time 1.42 seconds
Started Feb 09 02:04:02 PM UTC 25
Finished Feb 09 02:04:05 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437073377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2437073377
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3726070369
Short name T224
Test name
Test status
Simulation time 74395391 ps
CPU time 0.81 seconds
Started Feb 09 02:04:02 PM UTC 25
Finished Feb 09 02:04:04 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726070369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3726070369
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.1899411155
Short name T219
Test name
Test status
Simulation time 47725217 ps
CPU time 0.91 seconds
Started Feb 09 02:04:01 PM UTC 25
Finished Feb 09 02:04:03 PM UTC 25
Peak memory 208472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899411155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1899411155
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.225993902
Short name T226
Test name
Test status
Simulation time 44061432 ps
CPU time 1.16 seconds
Started Feb 09 02:04:02 PM UTC 25
Finished Feb 09 02:04:04 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225993902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.225993902
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.1196924047
Short name T215
Test name
Test status
Simulation time 72530122 ps
CPU time 1.07 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:02 PM UTC 25
Peak memory 208460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196924047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.1196924047
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.3635334824
Short name T213
Test name
Test status
Simulation time 73864912 ps
CPU time 1.16 seconds
Started Feb 09 02:03:59 PM UTC 25
Finished Feb 09 02:04:01 PM UTC 25
Peak memory 210836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635334824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3635334824
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.1872759006
Short name T225
Test name
Test status
Simulation time 308909841 ps
CPU time 1.24 seconds
Started Feb 09 02:04:02 PM UTC 25
Finished Feb 09 02:04:04 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872759006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1872759006
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1531402903
Short name T223
Test name
Test status
Simulation time 330280067 ps
CPU time 1.27 seconds
Started Feb 09 02:04:01 PM UTC 25
Finished Feb 09 02:04:03 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531402903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.1531402903
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.743461578
Short name T228
Test name
Test status
Simulation time 717595728 ps
CPU time 3.25 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:05 PM UTC 25
Peak memory 211436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743461578 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.743461578
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.566084587
Short name T227
Test name
Test status
Simulation time 936123617 ps
CPU time 3.02 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:05 PM UTC 25
Peak memory 211364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566084587 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.566084587
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.925008009
Short name T222
Test name
Test status
Simulation time 123270243 ps
CPU time 1.2 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:03 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925008009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.925008009
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1183071837
Short name T139
Test name
Test status
Simulation time 33596974 ps
CPU time 0.75 seconds
Started Feb 09 02:03:59 PM UTC 25
Finished Feb 09 02:04:01 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183071837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1183071837
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.946748259
Short name T111
Test name
Test status
Simulation time 1334676485 ps
CPU time 5.97 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:11 PM UTC 25
Peak memory 211568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946748259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.946748259
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.198013003
Short name T46
Test name
Test status
Simulation time 9433074290 ps
CPU time 35.31 seconds
Started Feb 09 02:04:02 PM UTC 25
Finished Feb 09 02:04:39 PM UTC 25
Peak memory 211712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=198013003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_r
eset.198013003
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.2868595346
Short name T216
Test name
Test status
Simulation time 260481843 ps
CPU time 1.04 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:02 PM UTC 25
Peak memory 208468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868595346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.2868595346
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3589740443
Short name T220
Test name
Test status
Simulation time 415364896 ps
CPU time 1.27 seconds
Started Feb 09 02:04:00 PM UTC 25
Finished Feb 09 02:04:03 PM UTC 25
Peak memory 210712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589740443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3589740443
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.3489191258
Short name T110
Test name
Test status
Simulation time 70410225 ps
CPU time 1.26 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:07 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489191258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.3489191258
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.1363190905
Short name T171
Test name
Test status
Simulation time 59518699 ps
CPU time 1.08 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:09 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363190905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.1363190905
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2627187822
Short name T162
Test name
Test status
Simulation time 45280805 ps
CPU time 0.92 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:08 PM UTC 25
Peak memory 206332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627187822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.2627187822
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.2233864139
Short name T163
Test name
Test status
Simulation time 158912240 ps
CPU time 1.86 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:09 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233864139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.2233864139
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3354700451
Short name T236
Test name
Test status
Simulation time 44393076 ps
CPU time 1.04 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:08 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354700451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3354700451
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.82345093
Short name T234
Test name
Test status
Simulation time 23469645 ps
CPU time 0.94 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:08 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82345093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.82345093
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.4177150938
Short name T194
Test name
Test status
Simulation time 83716289 ps
CPU time 0.9 seconds
Started Feb 09 02:04:08 PM UTC 25
Finished Feb 09 02:04:10 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177150938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.4177150938
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.962248907
Short name T233
Test name
Test status
Simulation time 264638221 ps
CPU time 2.11 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:07 PM UTC 25
Peak memory 210856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962248907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.962248907
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.2824014952
Short name T230
Test name
Test status
Simulation time 97913395 ps
CPU time 1.08 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:06 PM UTC 25
Peak memory 210836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824014952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.2824014952
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1483397025
Short name T240
Test name
Test status
Simulation time 113680944 ps
CPU time 1.41 seconds
Started Feb 09 02:04:08 PM UTC 25
Finished Feb 09 02:04:10 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483397025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1483397025
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.3872601346
Short name T235
Test name
Test status
Simulation time 122410725 ps
CPU time 1.13 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:08 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872601346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.3872601346
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.223085253
Short name T241
Test name
Test status
Simulation time 930022863 ps
CPU time 5.5 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:11 PM UTC 25
Peak memory 211180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223085253 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.223085253
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1572920478
Short name T238
Test name
Test status
Simulation time 1014798292 ps
CPU time 4.19 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:10 PM UTC 25
Peak memory 211668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572920478 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1572920478
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.927290990
Short name T237
Test name
Test status
Simulation time 51752087 ps
CPU time 1.37 seconds
Started Feb 09 02:04:06 PM UTC 25
Finished Feb 09 02:04:09 PM UTC 25
Peak memory 208372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927290990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.927290990
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.1087910500
Short name T229
Test name
Test status
Simulation time 40820146 ps
CPU time 1.03 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:06 PM UTC 25
Peak memory 208492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087910500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1087910500
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.719824477
Short name T112
Test name
Test status
Simulation time 1529237978 ps
CPU time 4.75 seconds
Started Feb 09 02:04:08 PM UTC 25
Finished Feb 09 02:04:14 PM UTC 25
Peak memory 211524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719824477 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.719824477
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3666969766
Short name T26
Test name
Test status
Simulation time 4284962016 ps
CPU time 7.44 seconds
Started Feb 09 02:04:08 PM UTC 25
Finished Feb 09 02:04:16 PM UTC 25
Peak memory 211544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=3666969766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_
reset.3666969766
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.4107153801
Short name T232
Test name
Test status
Simulation time 264182731 ps
CPU time 1.31 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:07 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107153801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.4107153801
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4232960467
Short name T231
Test name
Test status
Simulation time 249583172 ps
CPU time 1.16 seconds
Started Feb 09 02:04:04 PM UTC 25
Finished Feb 09 02:04:07 PM UTC 25
Peak memory 210684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232960467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.4232960467
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2848599806
Short name T245
Test name
Test status
Simulation time 31613621 ps
CPU time 1.2 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:12 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848599806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2848599806
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.4235442442
Short name T250
Test name
Test status
Simulation time 62803215 ps
CPU time 1.03 seconds
Started Feb 09 02:04:12 PM UTC 25
Finished Feb 09 02:04:14 PM UTC 25
Peak memory 210716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235442442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.4235442442
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2022749816
Short name T164
Test name
Test status
Simulation time 39834503 ps
CPU time 0.9 seconds
Started Feb 09 02:04:11 PM UTC 25
Finished Feb 09 02:04:13 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022749816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.2022749816
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.776150929
Short name T253
Test name
Test status
Simulation time 621286479 ps
CPU time 1.4 seconds
Started Feb 09 02:04:11 PM UTC 25
Finished Feb 09 02:04:14 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776150929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc
alation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.776150929
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.294749007
Short name T247
Test name
Test status
Simulation time 59755732 ps
CPU time 0.83 seconds
Started Feb 09 02:04:11 PM UTC 25
Finished Feb 09 02:04:13 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294749007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.294749007
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2804208025
Short name T248
Test name
Test status
Simulation time 25572403 ps
CPU time 0.92 seconds
Started Feb 09 02:04:11 PM UTC 25
Finished Feb 09 02:04:13 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804208025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2804208025
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.2696647132
Short name T255
Test name
Test status
Simulation time 85756272 ps
CPU time 0.88 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:15 PM UTC 25
Peak memory 211068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696647132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.2696647132
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1485114644
Short name T243
Test name
Test status
Simulation time 248302431 ps
CPU time 1.28 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:11 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485114644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.1485114644
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.2660063120
Short name T242
Test name
Test status
Simulation time 86000564 ps
CPU time 1.06 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:11 PM UTC 25
Peak memory 210832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660063120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.2660063120
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1349122751
Short name T257
Test name
Test status
Simulation time 109864595 ps
CPU time 1.1 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:15 PM UTC 25
Peak memory 220204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349122751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1349122751
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1313808325
Short name T249
Test name
Test status
Simulation time 69020525 ps
CPU time 0.96 seconds
Started Feb 09 02:04:11 PM UTC 25
Finished Feb 09 02:04:14 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313808325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.1313808325
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.945525553
Short name T254
Test name
Test status
Simulation time 933540958 ps
CPU time 4.49 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:15 PM UTC 25
Peak memory 211372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945525553 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.945525553
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3172464158
Short name T252
Test name
Test status
Simulation time 1194382345 ps
CPU time 3.51 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:14 PM UTC 25
Peak memory 211432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172464158 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3172464158
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3797391772
Short name T251
Test name
Test status
Simulation time 118386822 ps
CPU time 1.34 seconds
Started Feb 09 02:04:11 PM UTC 25
Finished Feb 09 02:04:14 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797391772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3797391772
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.413589541
Short name T239
Test name
Test status
Simulation time 55969380 ps
CPU time 0.96 seconds
Started Feb 09 02:04:08 PM UTC 25
Finished Feb 09 02:04:10 PM UTC 25
Peak memory 208536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413589541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.413589541
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.2172366844
Short name T92
Test name
Test status
Simulation time 860955510 ps
CPU time 3.52 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:18 PM UTC 25
Peak memory 211512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172366844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.2172366844
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.914221412
Short name T130
Test name
Test status
Simulation time 3677364665 ps
CPU time 17.84 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:32 PM UTC 25
Peak memory 211548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=914221412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_r
eset.914221412
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4007702395
Short name T244
Test name
Test status
Simulation time 73471304 ps
CPU time 1.25 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:11 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007702395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.4007702395
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.3033425179
Short name T246
Test name
Test status
Simulation time 247104961 ps
CPU time 1.94 seconds
Started Feb 09 02:04:09 PM UTC 25
Finished Feb 09 02:04:12 PM UTC 25
Peak memory 210888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033425179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.3033425179
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1421599473
Short name T87
Test name
Test status
Simulation time 124540998 ps
CPU time 1.02 seconds
Started Feb 09 02:04:15 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421599473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1421599473
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.142912001
Short name T192
Test name
Test status
Simulation time 66226882 ps
CPU time 1.31 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:19 PM UTC 25
Peak memory 210780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142912001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.142912001
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.4174546900
Short name T88
Test name
Test status
Simulation time 37468924 ps
CPU time 0.91 seconds
Started Feb 09 02:04:15 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 206380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174546900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.4174546900
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.2719507607
Short name T263
Test name
Test status
Simulation time 167143015 ps
CPU time 1.62 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:19 PM UTC 25
Peak memory 206432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719507607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2719507607
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3745099788
Short name T94
Test name
Test status
Simulation time 34320994 ps
CPU time 0.8 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:18 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745099788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3745099788
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1465896777
Short name T93
Test name
Test status
Simulation time 100998812 ps
CPU time 0.85 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:18 PM UTC 25
Peak memory 206424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465896777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1465896777
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.969723563
Short name T260
Test name
Test status
Simulation time 71470516 ps
CPU time 0.92 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:19 PM UTC 25
Peak memory 211072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969723563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.969723563
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2196402834
Short name T259
Test name
Test status
Simulation time 292991577 ps
CPU time 1.42 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:16 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196402834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.2196402834
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.9337180
Short name T214
Test name
Test status
Simulation time 60996397 ps
CPU time 1.35 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:16 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9337180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.9337180
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.963527864
Short name T262
Test name
Test status
Simulation time 96720959 ps
CPU time 1.25 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:19 PM UTC 25
Peak memory 220144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963527864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.963527864
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.37840218
Short name T90
Test name
Test status
Simulation time 471726878 ps
CPU time 1.17 seconds
Started Feb 09 02:04:15 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37840218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.37840218
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997111464
Short name T261
Test name
Test status
Simulation time 1207897818 ps
CPU time 3.1 seconds
Started Feb 09 02:04:15 PM UTC 25
Finished Feb 09 02:04:19 PM UTC 25
Peak memory 211292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997111464 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997111464
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3745637175
Short name T95
Test name
Test status
Simulation time 1080360292 ps
CPU time 2.76 seconds
Started Feb 09 02:04:15 PM UTC 25
Finished Feb 09 02:04:19 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745637175 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3745637175
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.319300767
Short name T91
Test name
Test status
Simulation time 50300549 ps
CPU time 1.33 seconds
Started Feb 09 02:04:15 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 208280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319300767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.319300767
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.1604198159
Short name T256
Test name
Test status
Simulation time 50227246 ps
CPU time 0.92 seconds
Started Feb 09 02:04:13 PM UTC 25
Finished Feb 09 02:04:15 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604198159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1604198159
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.2578589045
Short name T101
Test name
Test status
Simulation time 1168765639 ps
CPU time 3.94 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 211356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578589045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.2578589045
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.4209461522
Short name T131
Test name
Test status
Simulation time 8522968078 ps
CPU time 17.97 seconds
Started Feb 09 02:04:16 PM UTC 25
Finished Feb 09 02:04:36 PM UTC 25
Peak memory 211932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=4209461522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_
reset.4209461522
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2053032881
Short name T217
Test name
Test status
Simulation time 132300366 ps
CPU time 1.11 seconds
Started Feb 09 02:04:14 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053032881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2053032881
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.725631751
Short name T258
Test name
Test status
Simulation time 123618009 ps
CPU time 1.43 seconds
Started Feb 09 02:04:14 PM UTC 25
Finished Feb 09 02:04:17 PM UTC 25
Peak memory 210712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725631751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.725631751
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2308903693
Short name T266
Test name
Test status
Simulation time 172685573 ps
CPU time 1.09 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:21 PM UTC 25
Peak memory 208348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308903693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_ab
orted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2308903693
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2783417983
Short name T99
Test name
Test status
Simulation time 52605548 ps
CPU time 1.34 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783417983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.2783417983
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1007274409
Short name T270
Test name
Test status
Simulation time 37941334 ps
CPU time 0.9 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:22 PM UTC 25
Peak memory 206492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007274409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.1007274409
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.4078780533
Short name T103
Test name
Test status
Simulation time 165039612 ps
CPU time 1.79 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078780533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_es
calation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.4078780533
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1802174749
Short name T272
Test name
Test status
Simulation time 82888296 ps
CPU time 0.9 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:22 PM UTC 25
Peak memory 206428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802174749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.1802174749
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.1888682800
Short name T273
Test name
Test status
Simulation time 24170529 ps
CPU time 0.96 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 206372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888682800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.1888682800
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.217036869
Short name T100
Test name
Test status
Simulation time 50362965 ps
CPU time 0.84 seconds
Started Feb 09 02:04:21 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 211132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217036869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.217036869
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.1887925475
Short name T267
Test name
Test status
Simulation time 275206413 ps
CPU time 1.35 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:21 PM UTC 25
Peak memory 208484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887925475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.1887925475
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.2702721606
Short name T269
Test name
Test status
Simulation time 84895190 ps
CPU time 1.57 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:21 PM UTC 25
Peak memory 210776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702721606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2702721606
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1372526582
Short name T98
Test name
Test status
Simulation time 155017942 ps
CPU time 1.23 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 220144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372526582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1372526582
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3274695947
Short name T102
Test name
Test status
Simulation time 293172860 ps
CPU time 1.84 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:23 PM UTC 25
Peak memory 211200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274695947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_te
st +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.3274695947
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3184257990
Short name T104
Test name
Test status
Simulation time 739309986 ps
CPU time 4.21 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:24 PM UTC 25
Peak memory 211444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184257990 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3184257990
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2083471909
Short name T105
Test name
Test status
Simulation time 940511497 ps
CPU time 3.21 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:25 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083471909 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2083471909
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3859753356
Short name T271
Test name
Test status
Simulation time 93906855 ps
CPU time 1.04 seconds
Started Feb 09 02:04:20 PM UTC 25
Finished Feb 09 02:04:22 PM UTC 25
Peak memory 208480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859753356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3859753356
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2666996103
Short name T264
Test name
Test status
Simulation time 29662478 ps
CPU time 1.01 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:20 PM UTC 25
Peak memory 208540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666996103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2666996103
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.666967873
Short name T291
Test name
Test status
Simulation time 1847416227 ps
CPU time 7.19 seconds
Started Feb 09 02:04:23 PM UTC 25
Finished Feb 09 02:04:31 PM UTC 25
Peak memory 211488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666967873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_
test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.666967873
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1493896694
Short name T59
Test name
Test status
Simulation time 6263938922 ps
CPU time 26.5 seconds
Started Feb 09 02:04:23 PM UTC 25
Finished Feb 09 02:04:50 PM UTC 25
Peak memory 211624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_str
ess_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_
random_seed=1493896694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_
reset.1493896694
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.3060037557
Short name T265
Test name
Test status
Simulation time 47438652 ps
CPU time 1.07 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:21 PM UTC 25
Peak memory 208476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060037557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.3060037557
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.4254047362
Short name T268
Test name
Test status
Simulation time 366538461 ps
CPU time 1.34 seconds
Started Feb 09 02:04:18 PM UTC 25
Finished Feb 09 02:04:21 PM UTC 25
Peak memory 210712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254047362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.4254047362
Directory /workspaces/repo/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest
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