PWRMGR Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 45.994s 44 50 88.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.640s 40.234us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 23.415s 18 20 90.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.120s 606.263us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.900s 43.443us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 23.563s 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 23.415s 18 20 90.00
pwrmgr_csr_aliasing 0.900s 43.443us 5 5 100.00
V1 TOTAL 96 105 91.43
V2 wakeup pwrmgr_wakeup 42.047s 45 50 90.00
V2 control_clks pwrmgr_wakeup 42.047s 45 50 90.00
V2 aborted_low_power pwrmgr_aborted_low_power 48.810s 45 50 90.00
pwrmgr_lowpower_invalid 1.073m 45 50 90.00
V2 reset pwrmgr_reset 49.231s 45 50 90.00
pwrmgr_reset_invalid 31.740s 47 50 94.00
V2 main_power_glitch_reset pwrmgr_reset 49.231s 45 50 90.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 49.984s 46 50 92.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 48.619s 45 50 90.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 51.982s 45 50 90.00
V2 stress_all pwrmgr_stress_all 1.090m 44 50 88.00
V2 intr_test pwrmgr_intr_test 23.333s 49 50 98.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 30.593s 18 20 90.00
V2 tl_d_illegal_access pwrmgr_tl_errors 30.593s 18 20 90.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.640s 40.234us 5 5 100.00
pwrmgr_csr_rw 23.415s 18 20 90.00
pwrmgr_csr_aliasing 0.900s 43.443us 5 5 100.00
pwrmgr_same_csr_outstanding 23.495s 18 20 90.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.640s 40.234us 5 5 100.00
pwrmgr_csr_rw 23.415s 18 20 90.00
pwrmgr_csr_aliasing 0.900s 43.443us 5 5 100.00
pwrmgr_same_csr_outstanding 23.495s 18 20 90.00
V2 TOTAL 492 540 91.11
V2S tl_intg_err pwrmgr_tl_intg_err 23.242s 19 20 95.00
pwrmgr_sec_cm 2.510s 672.882us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.510s 672.882us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.510s 672.882us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 23.242s 19 20 95.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 51.314s 43 50 86.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 49.874s 45 50 90.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 51.245s 42 50 84.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 44.405s 45 50 90.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.510s 672.882us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.510s 672.882us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.510s 672.882us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 48.452s 45 50 90.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 37.177s 45 50 90.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 58.328s 44 50 88.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 23.415s 18 20 90.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 23.415s 18 20 90.00
V2S TOTAL 333 375 88.80
V3 escalation_timeout pwrmgr_escalation_timeout 42.037s 48 50 96.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 55.687s 40 50 80.00
V3 TOTAL 88 100 88.00
TOTAL 1009 1120 90.09

Testplan Progress

Items Total Written Passing Progress
V1 6 6 3 50.00
V2 12 12 0 0.00
V2S 9 9 1 11.11
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.21 96.58 99.62 96.00 96.32 100.00 98.69

Failure Buckets

Past Results