PWRMGR Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 42.332s 46 50 92.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.660s 78.449us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.670s 47.892us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.050s 305.074us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.750s 90.269us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.450s 80.610us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.670s 47.892us 20 20 100.00
pwrmgr_csr_aliasing 0.750s 90.269us 5 5 100.00
V1 TOTAL 101 105 96.19
V2 wakeup pwrmgr_wakeup 48.296s 45 50 90.00
V2 control_clks pwrmgr_wakeup 48.296s 45 50 90.00
V2 aborted_low_power pwrmgr_aborted_low_power 44.808s 46 50 92.00
pwrmgr_lowpower_invalid 1.037m 6 50 12.00
V2 reset pwrmgr_reset 42.306s 46 50 92.00
pwrmgr_reset_invalid 1.019m 47 50 94.00
V2 main_power_glitch_reset pwrmgr_reset 42.306s 46 50 92.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 44.826s 44 50 88.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 42.279s 46 50 92.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 41.396s 47 50 94.00
V2 stress_all pwrmgr_stress_all 45.032s 46 50 92.00
V2 intr_test pwrmgr_intr_test 21.940s 49 50 98.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 33.066s 19 20 95.00
V2 tl_d_illegal_access pwrmgr_tl_errors 33.066s 19 20 95.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.660s 78.449us 5 5 100.00
pwrmgr_csr_rw 0.670s 47.892us 20 20 100.00
pwrmgr_csr_aliasing 0.750s 90.269us 5 5 100.00
pwrmgr_same_csr_outstanding 34.961s 19 20 95.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.660s 78.449us 5 5 100.00
pwrmgr_csr_rw 0.670s 47.892us 20 20 100.00
pwrmgr_csr_aliasing 0.750s 90.269us 5 5 100.00
pwrmgr_same_csr_outstanding 34.961s 19 20 95.00
V2 TOTAL 460 540 85.19
V2S tl_intg_err pwrmgr_tl_intg_err 33.055s 18 20 90.00
pwrmgr_sec_cm 1.890s 769.168us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.890s 769.168us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.890s 769.168us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 33.055s 18 20 90.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 58.060s 46 50 92.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 59.264s 46 50 92.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.022m 47 50 94.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 46.988s 47 50 94.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.890s 769.168us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.890s 769.168us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.890s 769.168us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 1.195m 45 50 90.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 59.142s 47 50 94.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.021m 44 50 88.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.670s 47.892us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.670s 47.892us 20 20 100.00
V2S TOTAL 345 375 92.00
V3 escalation_timeout pwrmgr_escalation_timeout 59.166s 45 50 90.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 42.378s 44 50 88.00
V3 TOTAL 89 100 89.00
TOTAL 995 1120 88.84

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 12 12 0 0.00
V2S 9 9 1 11.11
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02

Failure Buckets

Past Results