PWRMGR Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	1.020s	29.681us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	1.070s	30.633us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	1.030s	67.502us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	4.350s	1.792ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.400s	86.291us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.880s	331.536us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	1.030s	67.502us	20	20	100.00
		pwrmgr_csr_aliasing	1.400s	86.291us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.920s	283.984us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.920s	283.984us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.630s	35.054us	50	50	100.00
		pwrmgr_lowpower_invalid	1.160s	38.738us	50	50	100.00
V2	reset	pwrmgr_reset	1.380s	100.422us	50	50	100.00
		pwrmgr_reset_invalid	1.500s	99.351us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.380s	100.422us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.880s	259.933us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.660s	258.239us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.340s	64.062us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.600s	2.042ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.980s	21.271us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.230s	814.105us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.230s	814.105us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	1.070s	30.633us	5	5	100.00
		pwrmgr_csr_rw	1.030s	67.502us	20	20	100.00
		pwrmgr_csr_aliasing	1.400s	86.291us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.300s	177.893us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	1.070s	30.633us	5	5	100.00
		pwrmgr_csr_rw	1.030s	67.502us	20	20	100.00
		pwrmgr_csr_aliasing	1.400s	86.291us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.300s	177.893us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.380s	218.358us	20	20	100.00
		pwrmgr_sec_cm	2.400s	589.145us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.400s	589.145us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.400s	589.145us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.380s	218.358us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.240s	801.326us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.180s	951.128us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.520s	65.227us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	1.050s	30.954us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.400s	589.145us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.400s	589.145us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.400s	589.145us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.910s	56.342us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.960s	61.785us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.900s	264.267us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	1.030s	67.502us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	1.030s	67.502us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.390s	213.361us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	19.180s	14.123ms	47	50	94.00
V3		TOTAL			97	100	97.00
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.96	98.21	96.58	99.62	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:771) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 2.pwrmgr_stress_all_with_rand_reset.83019807703259128530308576575212442181815580312928201461918049804355048655130
      Line 1563, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3036450993 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3036450993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.pwrmgr_stress_all_with_rand_reset.54424140311004329064582376631090315113406955676415840682840229702559757749986
      Line 3899, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 30782372932 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 30782372932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:101) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 46.pwrmgr_stress_all_with_rand_reset.39315449805014017998138675286512894680494813866119642699843810969556766616754
      Line 2094, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 12153633466 ps: (cip_base_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 12153633466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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