PWRMGR Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	1.050s	30.793us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	1.000s	224.124us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	1.030s	19.683us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.290s	221.156us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.220s	129.657us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.520s	51.578us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	1.030s	19.683us	20	20	100.00
		pwrmgr_csr_aliasing	1.220s	129.657us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	2.270s	202.483us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	2.270s	202.483us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.430s	51.008us	50	50	100.00
		pwrmgr_lowpower_invalid	1.070s	15.985us	1	50	2.00
V2	reset	pwrmgr_reset	1.490s	70.678us	50	50	100.00
		pwrmgr_reset_invalid	1.630s	106.773us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.490s	70.678us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	2.200s	334.481us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.690s	271.078us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.390s	65.081us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.930s	2.001ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.950s	24.344us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.330s	627.797us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.330s	627.797us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	1.000s	224.124us	5	5	100.00
		pwrmgr_csr_rw	1.030s	19.683us	20	20	100.00
		pwrmgr_csr_aliasing	1.220s	129.657us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.290s	111.626us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	1.000s	224.124us	5	5	100.00
		pwrmgr_csr_rw	1.030s	19.683us	20	20	100.00
		pwrmgr_csr_aliasing	1.220s	129.657us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.290s	111.626us	20	20	100.00
V2		TOTAL			491	540	90.93
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.520s	193.039us	20	20	100.00
		pwrmgr_sec_cm	3.240s	661.842us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	3.240s	661.842us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	3.240s	661.842us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.520s	193.039us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.980s	738.077us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.990s	866.801us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.510s	114.490us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.980s	31.720us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	3.240s	661.842us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	3.240s	661.842us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	3.240s	661.842us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	1.010s	33.445us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	1.040s	34.262us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.890s	299.778us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	1.030s	19.683us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	1.030s	19.683us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.430s	623.715us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	20.280s	6.118ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1070	1120	95.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.96	98.21	96.58	99.62	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*]) has 48 failures:

  • Test pwrmgr_lowpower_invalid has 48 failures.

    • 0.pwrmgr_lowpower_invalid.93457763716501404611767655445197294812421893942432372394302448738640560236065
      Line 69, in log /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest/run.log

        UVM_ERROR @  15985034 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @  15985034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.pwrmgr_lowpower_invalid.22283616012345833523082097545339168734953047848209827919380559265454443611470
      Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest/run.log

        UVM_ERROR @  36511097 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @  36511097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 46 more failures.

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 24.pwrmgr_lowpower_invalid.52572793689369590546376773701791564962994844925915741330743077883194429423663
      Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  38987332 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  38987332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 25.pwrmgr_stress_all_with_rand_reset.100542576740790905618280277337043629262687555588822124116400316481166960536279
      Line 1972, in log /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1452543694 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 1452543694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.09.19_09.10.11
• 2024.09.12_10.21.50
• 2024.09.10_08.16.30
• 2024.09.05_04.26.10
• 2024.09.02_11.35.46
• 2024.08.29_23.17.54