RSTMGR Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 50.179s 47 50 94.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.020s 108.196us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.060s 74.992us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.520s 2.293ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.310s 430.361us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.700s 187.322us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.060s 74.992us 20 20 100.00
rstmgr_csr_aliasing 2.310s 430.361us 5 5 100.00
V1 TOTAL 102 105 97.14
V2 reset_stretcher rstmgr_por_stretcher 48.368s 48 50 96.00
V2 sw_rst rstmgr_sw_rst 46.250s 48 50 96.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 42.686s 49 50 98.00
V2 reset_info rstmgr_reset 42.711s 48 50 96.00
V2 cpu_info rstmgr_reset 42.711s 48 50 96.00
V2 alert_info rstmgr_reset 42.711s 48 50 96.00
V2 reset_info_capture rstmgr_reset 42.711s 48 50 96.00
V2 stress_all rstmgr_stress_all 42.822s 48 50 96.00
V2 alert_test rstmgr_alert_test 50.199s 48 50 96.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.520s 570.578us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.520s 570.578us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.020s 108.196us 5 5 100.00
rstmgr_csr_rw 1.060s 74.992us 20 20 100.00
rstmgr_csr_aliasing 2.310s 430.361us 5 5 100.00
rstmgr_same_csr_outstanding 1.640s 210.274us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.020s 108.196us 5 5 100.00
rstmgr_csr_rw 1.060s 74.992us 20 20 100.00
rstmgr_csr_aliasing 2.310s 430.361us 5 5 100.00
rstmgr_same_csr_outstanding 1.640s 210.274us 20 20 100.00
V2 TOTAL 329 340 96.76
V2S tl_intg_err rstmgr_sec_cm 29.410s 16.521ms 5 5 100.00
rstmgr_tl_intg_err 3.850s 1.202ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 29.410s 16.521ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 29.410s 16.521ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.850s 1.202ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 48.524s 47 50 94.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 48.507s 47 50 94.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 48.482s 47 50 94.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 29.410s 16.521ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.060s 74.992us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.060s 74.992us 20 20 100.00
V2S TOTAL 166 175 94.86
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 597 620 96.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 8 8 2 25.00
V2S 5 5 2 40.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Failure Buckets

Past Results