RSTMGR Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.180s 254.320us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.050s 134.743us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.070s 62.867us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 12.430s 2.309ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.450s 358.816us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.350s 161.151us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.070s 62.867us 20 20 100.00
rstmgr_csr_aliasing 2.450s 358.816us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.470s 191.531us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 3.190s 456.118us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.990s 181.523us 50 50 100.00
V2 reset_info rstmgr_reset 9.290s 2.220ms 50 50 100.00
V2 cpu_info rstmgr_reset 9.290s 2.220ms 50 50 100.00
V2 alert_info rstmgr_reset 9.290s 2.220ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 9.290s 2.220ms 50 50 100.00
V2 stress_all rstmgr_stress_all 58.380s 15.956ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.250s 88.500us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.230s 460.621us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.230s 460.621us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.050s 134.743us 5 5 100.00
rstmgr_csr_rw 1.070s 62.867us 20 20 100.00
rstmgr_csr_aliasing 2.450s 358.816us 5 5 100.00
rstmgr_same_csr_outstanding 1.650s 228.568us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.050s 134.743us 5 5 100.00
rstmgr_csr_rw 1.070s 62.867us 20 20 100.00
rstmgr_csr_aliasing 2.450s 358.816us 5 5 100.00
rstmgr_same_csr_outstanding 1.650s 228.568us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 36.150s 16.506ms 5 5 100.00
rstmgr_tl_intg_err 7.520s 2.694ms 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 36.150s 16.506ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 36.150s 16.506ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 7.520s 2.694ms 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.780s 186.689us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 10.750s 2.443ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.760s 303.027us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 36.150s 16.506ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.070s 62.867us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.070s 62.867us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.45 99.40 99.24 100.00 -- 99.83 99.46 98.77

Past Results