RSTMGR Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.710s 250.405us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.330s 98.246us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.390s 92.908us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 5.970s 491.402us 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 3.060s 267.863us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.180s 204.822us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.390s 92.908us 20 20 100.00
rstmgr_csr_aliasing 3.060s 267.863us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.700s 221.157us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 4.590s 537.202us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.340s 232.542us 50 50 100.00
V2 reset_info rstmgr_reset 12.910s 2.044ms 50 50 100.00
V2 cpu_info rstmgr_reset 12.910s 2.044ms 50 50 100.00
V2 alert_info rstmgr_reset 12.910s 2.044ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 12.910s 2.044ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.059m 16.257ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.690s 164.706us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.920s 510.199us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.920s 510.199us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.330s 98.246us 5 5 100.00
rstmgr_csr_rw 1.390s 92.908us 20 20 100.00
rstmgr_csr_aliasing 3.060s 267.863us 5 5 100.00
rstmgr_same_csr_outstanding 2.320s 211.163us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.330s 98.246us 5 5 100.00
rstmgr_csr_rw 1.390s 92.908us 20 20 100.00
rstmgr_csr_aliasing 3.060s 267.863us 5 5 100.00
rstmgr_same_csr_outstanding 2.320s 211.163us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 46.610s 16.564ms 5 5 100.00
rstmgr_tl_intg_err 3.990s 943.831us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 46.610s 16.564ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 46.610s 16.564ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.990s 943.831us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 2.060s 186.208us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 14.470s 2.456ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 2.340s 301.949us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 46.610s 16.564ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.390s 92.908us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.390s 92.908us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Past Results