RSTMGR Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.470s 249.454us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.600s 145.984us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.430s 85.523us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.620s 1.024ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 3.930s 343.958us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.540s 161.028us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.430s 85.523us 20 20 100.00
rstmgr_csr_aliasing 3.930s 343.958us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.690s 211.983us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 4.960s 512.901us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.640s 307.738us 50 50 100.00
V2 reset_info rstmgr_reset 12.420s 1.840ms 50 50 100.00
V2 cpu_info rstmgr_reset 12.420s 1.840ms 50 50 100.00
V2 alert_info rstmgr_reset 12.420s 1.840ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 12.420s 1.840ms 50 50 100.00
V2 stress_all rstmgr_stress_all 1.413m 20.356ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.450s 138.327us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 5.060s 513.241us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 5.060s 513.241us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.600s 145.984us 5 5 100.00
rstmgr_csr_rw 1.430s 85.523us 20 20 100.00
rstmgr_csr_aliasing 3.930s 343.958us 5 5 100.00
rstmgr_same_csr_outstanding 2.570s 215.024us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.600s 145.984us 5 5 100.00
rstmgr_csr_rw 1.430s 85.523us 20 20 100.00
rstmgr_csr_aliasing 3.930s 343.958us 5 5 100.00
rstmgr_same_csr_outstanding 2.570s 215.024us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 44.490s 16.717ms 5 5 100.00
rstmgr_tl_intg_err 5.470s 970.965us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 44.490s 16.717ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 44.490s 16.717ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 5.470s 970.965us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 2.030s 170.204us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 14.080s 2.262ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 2.240s 301.869us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 44.490s 16.717ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.430s 85.523us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.430s 85.523us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Past Results