RSTMGR Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 2.580s 263.664us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.500s 117.948us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 1.280s 73.785us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 10.340s 2.312ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.570s 363.914us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.350s 188.489us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 1.280s 73.785us 20 20 100.00
rstmgr_csr_aliasing 2.570s 363.914us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.700s 208.152us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 4.330s 526.280us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 2.210s 226.025us 50 50 100.00
V2 reset_info rstmgr_reset 9.430s 2.021ms 50 50 100.00
V2 cpu_info rstmgr_reset 9.430s 2.021ms 50 50 100.00
V2 alert_info rstmgr_reset 9.430s 2.021ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 9.430s 2.021ms 50 50 100.00
V2 stress_all rstmgr_stress_all 50.740s 14.553ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.440s 86.992us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.920s 447.834us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.920s 447.834us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.500s 117.948us 5 5 100.00
rstmgr_csr_rw 1.280s 73.785us 20 20 100.00
rstmgr_csr_aliasing 2.570s 363.914us 5 5 100.00
rstmgr_same_csr_outstanding 2.170s 238.249us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.500s 117.948us 5 5 100.00
rstmgr_csr_rw 1.280s 73.785us 20 20 100.00
rstmgr_csr_aliasing 2.570s 363.914us 5 5 100.00
rstmgr_same_csr_outstanding 2.170s 238.249us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 29.900s 16.746ms 5 5 100.00
rstmgr_tl_intg_err 4.020s 916.991us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 29.900s 16.746ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 29.900s 16.746ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 4.020s 916.991us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 2.040s 184.115us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 11.770s 2.267ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 2.270s 301.199us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 29.900s 16.746ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 1.280s 73.785us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 1.280s 73.785us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.46 99.40 99.31 100.00 -- 99.83 99.46 98.77

Past Results