KEYMGR Simulation Results

Saturday June 01 2024 19:02:43 UTC

GitHub Revision: eb6a0f1711

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1841380615

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.206m 14.923ms 50 50 100.00
V1 random keymgr_random 56.000s 1.899ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.160s 39.030us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.390s 90.263us 14 20 70.00
V1 csr_bit_bash keymgr_csr_bit_bash 27.120s 1.193ms 3 5 60.00
V1 csr_aliasing keymgr_csr_aliasing 9.070s 370.793us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.110s 121.222us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.390s 90.263us 14 20 70.00
keymgr_csr_aliasing 9.070s 370.793us 5 5 100.00
V1 TOTAL 147 155 94.84
V2 cfgen_during_op keymgr_cfg_regwen 2.657m 5.006ms 50 50 100.00
V2 sideload keymgr_sideload 1.045m 3.460ms 50 50 100.00
keymgr_sideload_kmac 40.870s 5.651ms 50 50 100.00
keymgr_sideload_aes 52.920s 2.207ms 50 50 100.00
keymgr_sideload_otbn 1.387m 11.882ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 49.570s 4.815ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 10.890s 1.169ms 48 50 96.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.654m 7.688ms 44 50 88.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.605m 5.225ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.288m 2.289ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 42.160s 1.740ms 50 50 100.00
V2 stress_all keymgr_stress_all 5.587m 36.130ms 49 50 98.00
V2 intr_test keymgr_intr_test 0.930s 14.676us 50 50 100.00
V2 alert_test keymgr_alert_test 1.180s 27.155us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.160s 878.615us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.160s 878.615us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.160s 39.030us 5 5 100.00
keymgr_csr_rw 1.390s 90.263us 14 20 70.00
keymgr_csr_aliasing 9.070s 370.793us 5 5 100.00
keymgr_same_csr_outstanding 2.540s 97.808us 14 20 70.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.160s 39.030us 5 5 100.00
keymgr_csr_rw 1.390s 90.263us 14 20 70.00
keymgr_csr_aliasing 9.070s 370.793us 5 5 100.00
keymgr_same_csr_outstanding 2.540s 97.808us 14 20 70.00
V2 TOTAL 725 740 97.97
V2S sec_cm_additional_check keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
keymgr_tl_intg_err 22.330s 1.287ms 12 20 60.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 33.310s 3.915ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 33.310s 3.915ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 33.310s 3.915ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 33.310s 3.915ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 12.170s 829.049us 10 20 50.00
V2S prim_count_check keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 22.330s 1.287ms 12 20 60.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 33.310s 3.915ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.657m 5.006ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 56.000s 1.899ms 50 50 100.00
keymgr_csr_rw 1.390s 90.263us 14 20 70.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 56.000s 1.899ms 50 50 100.00
keymgr_csr_rw 1.390s 90.263us 14 20 70.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 56.000s 1.899ms 50 50 100.00
keymgr_csr_rw 1.390s 90.263us 14 20 70.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 10.890s 1.169ms 48 50 96.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.288m 2.289ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.288m 2.289ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 56.000s 1.899ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 48.120s 6.396ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 47.610s 4.018ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 10.890s 1.169ms 48 50 96.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 47.610s 4.018ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 47.610s 4.018ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 47.610s 4.018ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 1.452m 9.100ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 47.610s 4.018ms 50 50 100.00
V2S TOTAL 147 165 89.09
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 17.100s 930.618us 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 1064 1110 95.86

Testplan Progress

Items Total Written Passing Progress
V1 7 7 5 71.43
V2 16 16 12 75.00
V2S 6 6 4 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.86 99.10 98.03 98.68 100.00 99.12 98.41 91.71

Failure Buckets

Past Results