KEYMGR_DPE Simulation Results

Saturday May 25 2024 19:02:40 UTC

GitHub Revision: 3216fab097

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1830339797

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_dpe_smoke 2.846m 31.872ms 49 50 98.00
V1 csr_hw_reset keymgr_dpe_csr_hw_reset 1.230s 85.586us 5 5 100.00
V1 csr_rw keymgr_dpe_csr_rw 1.450s 189.259us 20 20 100.00
V1 csr_bit_bash keymgr_dpe_csr_bit_bash 17.020s 596.690us 5 5 100.00
V1 csr_aliasing keymgr_dpe_csr_aliasing 10.290s 1.191ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_dpe_csr_mem_rw_with_rand_reset 1.700s 30.022us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_dpe_csr_rw 1.450s 189.259us 20 20 100.00
keymgr_dpe_csr_aliasing 10.290s 1.191ms 5 5 100.00
V1 TOTAL 104 105 99.05
V2 intr_test keymgr_dpe_intr_test 0.950s 14.711us 50 50 100.00
V2 alert_test keymgr_dpe_alert_test 1.090s 99.755us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_dpe_tl_errors 3.970s 224.183us 20 20 100.00
V2 tl_d_illegal_access keymgr_dpe_tl_errors 3.970s 224.183us 20 20 100.00
V2 tl_d_outstanding_access keymgr_dpe_csr_hw_reset 1.230s 85.586us 5 5 100.00
keymgr_dpe_csr_rw 1.450s 189.259us 20 20 100.00
keymgr_dpe_csr_aliasing 10.290s 1.191ms 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.400s 91.489us 20 20 100.00
V2 tl_d_partial_access keymgr_dpe_csr_hw_reset 1.230s 85.586us 5 5 100.00
keymgr_dpe_csr_rw 1.450s 189.259us 20 20 100.00
keymgr_dpe_csr_aliasing 10.290s 1.191ms 5 5 100.00
keymgr_dpe_same_csr_outstanding 2.400s 91.489us 20 20 100.00
V2 TOTAL 140 140 100.00
V2S tl_intg_err keymgr_dpe_sec_cm 24.210s 986.281us 5 5 100.00
keymgr_dpe_tl_intg_err 8.160s 910.412us 20 20 100.00
V2S shadow_reg_update_error keymgr_dpe_shadow_reg_errors 2.900s 180.222us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_dpe_shadow_reg_errors 2.900s 180.222us 20 20 100.00
V2S shadow_reg_storage_error keymgr_dpe_shadow_reg_errors 2.900s 180.222us 20 20 100.00
V2S shadowed_reset_glitch keymgr_dpe_shadow_reg_errors 2.900s 180.222us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_dpe_shadow_reg_errors_with_csr_rw 7.620s 841.635us 20 20 100.00
V2S prim_count_check keymgr_dpe_sec_cm 24.210s 986.281us 5 5 100.00
V2S prim_fsm_check keymgr_dpe_sec_cm 24.210s 986.281us 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset keymgr_dpe_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 309 310 99.68

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 4 4 4 100.00
V2S 4 4 4 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.24 97.60 90.55 57.52 76.92 94.97 98.34 17.82

Failure Buckets

Past Results