ADC_CTRL Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.110s	6.026ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.040s	1.027ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.670s	395.297us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.705m	26.174ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.970s	924.815us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.000s	505.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.670s	395.297us	20	20	100.00
		adc_ctrl_csr_aliasing	3.970s	924.815us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.083m	491.511ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.530m	487.897ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	18.027m	490.813ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.572m	501.287ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.021m	511.783ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.169m	496.246ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.866m	498.997ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.944m	498.250ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	12.630s	5.479ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.714m	41.510ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.014m	123.061ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	31.741m	542.238ms	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	1.760s	522.770us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.950s	480.573us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.550s	612.207us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.550s	612.207us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.040s	1.027ms	5	5	100.00
		adc_ctrl_csr_rw	1.670s	395.297us	20	20	100.00
		adc_ctrl_csr_aliasing	3.970s	924.815us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.520s	4.852ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.040s	1.027ms	5	5	100.00
		adc_ctrl_csr_rw	1.670s	395.297us	20	20	100.00
		adc_ctrl_csr_aliasing	3.970s	924.815us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.520s	4.852ms	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	tl_intg_err	adc_ctrl_sec_cm	16.810s	7.215ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.420s	8.759ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.420s	8.759ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.479m	438.396ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			892	920	96.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	99.01	95.70	100.00	100.00	98.18	98.64	91.44

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 23 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 3.adc_ctrl_stress_all_with_rand_reset.215529228
    Line 343, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 24243844769 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 24243844769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 4.adc_ctrl_stress_all_with_rand_reset.2487090721
    Line 418, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 336892881274 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 336892881274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 21 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 5 failures:

Test adc_ctrl_stress_all has 5 failures.

5.adc_ctrl_stress_all.3335078710
Line 347, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 481645924286 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 481645924286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.adc_ctrl_stress_all.1549842941
Line 345, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 488795420287 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 488795420287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.