ADC_CTRL Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.240s	5.816ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.530s	1.172ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	407.095us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.985m	52.321ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.210s	1.130ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.290s	575.402us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	407.095us	20	20	100.00
		adc_ctrl_csr_aliasing	5.210s	1.130ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.651m	490.579ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.175m	495.235ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.389m	485.756ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	21.027m	500.969ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.903m	505.329ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.226m	492.833ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.150m	476.319ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	18.084m	489.037ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.520s	5.315ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.816m	44.339ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.173m	132.441ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.161m	462.369ms	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	1.830s	532.280us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.790s	504.704us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.490s	616.399us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.490s	616.399us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.530s	1.172ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	407.095us	20	20	100.00
		adc_ctrl_csr_aliasing	5.210s	1.130ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.830s	5.198ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.530s	1.172ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	407.095us	20	20	100.00
		adc_ctrl_csr_aliasing	5.210s	1.130ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.830s	5.198ms	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	tl_intg_err	adc_ctrl_sec_cm	19.370s	8.105ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.340s	8.482ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.340s	8.482ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	17.680m	716.270ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			917	920	99.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	98.98	95.69	100.00	100.00	98.18	98.64	91.62

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 3 failures:
  • Test adc_ctrl_stress_all has 3 failures.

    • 7.adc_ctrl_stress_all.95097655153819850012595196479772630953102548226770211457065300441295388430367
      Line 373, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 340530065173 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 340530065173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.adc_ctrl_stress_all.67666126838997308266293323999326729290271185561114924679675747670982538355465
      Line 372, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 335331254100 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 335331254100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

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